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Technical

2 years ago

How would you describe the UVM RAL model and its role in UVM?

Design Verification Engineer

Apple

Sumitomo Electric

KLA

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2 years ago

Design

2 years ago

What is your approach to developing a 3 bit shift register using verilog RTL?

Design Verification Engineer

Apple

NETGEAR

Infineon

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2 years ago

Technical

2 years ago

Can you elucidate polymorphism as it applies to SystemVerilog?

Design Verification Engineer

Apple

MediaTek

Samsung

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2 years ago

Verilog Coding

2 years ago

How would you differentiate rand from randc in SystemVerilog, and can you give an example of each?

Design Verification Engineer

Apple

STMicroelectronics

Panasonic

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2 years ago

Technical

2 years ago

What are the distinct characteristics that differentiate RISC from CISC?

Design Verification Engineer

Apple

SpaceX

TP-Link

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2 years ago

Circuits

2 years ago

How would you describe a shift register and its functioning, supported by a circuit diagram?

Design Verification Engineer

Apple

OMRON

Canon

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2 years ago

Circuits

2 years ago

How would you construct an algorithm using just write(addr, data) and read(addr, &data) APIs to find a shorted internal signal, given no access to the signals themselves?

Design Verification Engineer

Apple

Legrand

Applied Materials

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2 years ago

Design

2 years ago

In your past work, how have you utilized bit manipulation? Could you give a specific example?

Design Verification Engineer

Apple

Silicon Labs

AT&T

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2 years ago

Computer Architecture

2 years ago

In computer architecture, how do a bus and a crossbar differ?

Design Verification Engineer

Apple

Dell

Western Digital

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2 years ago

Design

2 years ago

How do you approach identifying and improving the critical path in digital design?

Design Verification Engineer

Apple

Bombardier

Silicon Labs

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2 years ago

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