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Technical

2 years ago

In UVM, how does the 'new' method differ from the 'create' method?

Design Verification Engineer

Apple

Fujitsu

GlobalFoundries

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2 years ago

Algorithms

2 years ago

Could you explain how to systematically arrange 10 integers in an increasing sequence?

Design Verification Engineer

Apple

Seagate Technology

ZTE

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2 years ago

DesignCircuits

2 years ago

What's your methodology for designing a circuit with adders and gates, and what are key considerations?

Design Verification Engineer

Apple

Amgen

ASUS

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2 years ago

Design

2 years ago

What steps constitute the RTL design flow?

Design Verification Engineer

Apple

Microsoft

Hitachi

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2 years ago

Verilog Coding

2 years ago

Develop a constraint that ensures 4 generated variables are unique.

Design Verification Engineer

Apple

SK Hynix

Sumitomo Electric

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2 years ago

Circuits

2 years ago

What's the outcome on the voltages of two parallel capacitors with different charges when the transistor between them is activated?

Design Verification Engineer

Apple

Dialog Semiconductor

Kingston Technology

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2 years ago

Algorithms

2 years ago

How do you approach the task of converting a hexadecimal number into binary?

Design Verification Engineer

Apple

ASML

Belkin

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2 years ago

Technical

2 years ago

In your view, how do the # and $timeformat directives differ in Verilog?

Design Verification Engineer

Apple

Aurora

General Electric

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2 years ago

Technical

2 years ago

What is the radix in the expression 121(r) = 144(8)?

Design Verification Engineer

Apple

Silicon Motion

AIRBUS

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2 years ago

Circuits

2 years ago

Characterize a memory array, expound on a sense amplifier's operations, and clarify the purpose of an equilibration circuit.

Design Verification Engineer

Apple

Cisco

Cisco Systems

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2 years ago

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