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Technical

4 years ago

Can you explain the unique purposes of the 'new' and 'create' methods in UVM?

Design Verification Engineer

Xilinx

Fujitsu

GlobalFoundries

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4 years ago

Technical

4 years ago

How would you define Verilog and SystemVerilog, and what distinguishes them from each other?

Design Verification Engineer

Xilinx

Bombardier

Oppo

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4 years ago

Design

4 years ago

Can you outline your process for designing state machines and sequence detectors for various applications? What are the essential design considerations and optimization tactics?

Design Verification Engineer

Xilinx

Thales

STMicroelectronics

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4 years ago

Behavioral

4 years ago

Recall a moment where you exhibited a high level of ownership in your work.

Design Verification EngineerEmbedded Engineer

Xilinx

Waymo

Polaris Industries

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4 years ago

Circuits

4 years ago

What sets positive edge-triggered flip-flops apart from their negative edge-triggered counterparts?

Design Verification Engineer

Xilinx

Peloton

Dell Technologies

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4 years ago

Technical

4 years ago

What makes a FinFET different from a traditional MOSFET?

Design Verification Engineer

Xilinx

Zoox

Synopsys

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4 years ago

Algorithms

4 years ago

Why is the Tomasulo Algorithm preferred in scheduling over others? Have you incorporated it into your work? Share an example and explain how it handles pipeline hazards.

Design Verification Engineer

Xilinx

Cisco Systems

Bosch

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4 years ago

DesignCircuits

4 years ago

What’s your plan for engineering a multi-bit FIFO circuit?

Design Verification Engineer

Xilinx

Northrop Grumman

Taiwan Semiconductor

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4 years ago

Algorithms

4 years ago

How can you develop two arrays of 10 elements, ensuring uniqueness in both?

Design Verification Engineer

Xilinx

Autodesk

TP-Link

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4 years ago

Design

4 years ago

Could you detail the working principle of master/slave agents on a shared bus, with reference to AXI or analogous protocols, especially regarding data integrity and bus contention avoidance?

Design Verification Engineer

Xilinx

Aurora

Teradyne

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4 years ago

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^*All interview questions are submitted by recent Xilinx Design Verification Engineer candidates, labelled and categorized by Prepfully, and then published after being verified by Design Verification Engineers at Xilinx.

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