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Technical

3 years ago

Could you explain the concept of a counter's modulus and the modulus of a decade counter?

Design Verification Engineer

Xilinx

Qualcomm

Microsoft

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3 years ago

Technical

3 years ago

What are the ideal conditions for using a lock-up latch?

Design Verification Engineer

Xilinx

Juul Labs

Lattice Semiconductor

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3 years ago

DesignCircuits

3 years ago

What is your strategy for creating a circuit using adders and gates, and which aspects do you focus on?

Design Verification Engineer

Xilinx

Amgen

ASUS

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3 years ago

Technical

3 years ago

What's your history with validation/prototype and synthesis in design projects? How do you tackle these aspects?

Design Verification Engineer

Xilinx

Juniper Networks

ABB

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3 years ago

Technical

3 years ago

Can you differentiate between the 'new' and 'create' methods in UVM?

Design Verification Engineer

Xilinx

Fujitsu

GlobalFoundries

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3 years ago

Technical

3 years ago

In simple terms, how does CAM (content addressable memory) function?

Design Verification Engineer

Xilinx

Bombardier

Analog Devices

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3 years ago

Technical

3 years ago

What techniques would you use to overcome setup and hold time violations?

Design Verification Engineer

Xilinx

Yamaha Motor Corporation

Pratt & Whitney

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3 years ago

Verilog Coding

3 years ago

What approach would you take to formulate an SVA in System Verilog that certifies a signal's transition from 0 to 1 precedes another's fall from 1 to 0?

Design Verification Engineer

Xilinx

Kawasaki Heavy Industries

Philips Healthcare

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3 years ago

Technical

3 years ago

How do you interpret the role and structure of a Testbench?

Design Verification Engineer

Xilinx

Broadcom

Philips Healthcare

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3 years ago

Verilog Coding

3 years ago

In your experience, how do you develop a behavioral model using Verilog?

Design Verification Engineer

Xilinx

Philips

Peloton

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3 years ago

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