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Algorithms

3 years ago

How do you plan to code a solution for reversing a linked list?

Design Verification Engineer

Cisco Systems

Intel

IBM

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3 years ago

Technical

3 years ago

How would you describe your experience in implementing and verifying arbitration logic, including any common obstacles?

Design Verification Engineer

Cisco Systems

Panasonic

Leidos

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3 years ago

Technical

3 years ago

Can you distinguish between module and class-based Testbenches?

Design Verification Engineer

Cisco Systems

Ford Motor Company

IBM

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3 years ago

Technical

3 years ago

What separates soft constraints from hard constraints in SystemVerilog, in your view?

Design Verification Engineer

Cisco Systems

Canon

Microchip Technology

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3 years ago

Technical

3 years ago

What typical complications arise with queues and what are your strategies for resolving them?

Design Verification Engineer

Cisco Systems

Dell Technologies

Amazon Web Services

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3 years ago

Design

3 years ago

In VLSI design, how would you differentiate between delay and slew rate?

Design Verification Engineer

Cisco Systems

Sony

Northrop Grumman

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3 years ago

Behavioral

3 years ago

What metrics would you use to define success?

Design Verification EngineerEmbedded Engineer

Cisco Systems

Amazon

Synopsys

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3 years ago

Verilog Coding

3 years ago

In your interpretation, what is the significance of "wire #10 a = b & c"?

Design Verification Engineer

Cisco Systems

Fujikura

BAE Systems

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3 years ago

Technical

3 years ago

Can you describe the role of Karnaugh maps in the simplification of Boolean expressions?

Design Verification Engineer

Cisco Systems

Agilent Technologies

Lam Research

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3 years ago

Circuits

3 years ago

How would you construct an algorithm using just write(addr, data) and read(addr, &data) APIs to find a shorted internal signal, given no access to the signals themselves?

Design Verification Engineer

Cisco Systems

Legrand

Applied Materials

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3 years ago

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