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Circuits
2 years ago
Can you describe the impact on the voltages of two parallel capacitors with different charges when the connecting transistor is turned on?
Design Verification Engineer

Cisco Systems

Dialog Semiconductor

Kingston Technology

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2 years ago
Design
2 years ago
What are the typical violations in your field and how do you strategize to avoid them?
Design Verification Engineer

Cisco Systems

Mentor Graphics Logo

Mentor Graphics

Sharp Logo

Sharp

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2 years ago
Design
2 years ago
What is the pin count of a TAP interface in a JTAG boundary scan, and what are these pins?
Design Verification Engineer

Cisco Systems

Belkin Logo

Belkin

Hitachi Logo

Hitachi

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2 years ago
Technical
2 years ago
Please explain what a cache is and the principle behind its functioning.
Design Verification Engineer

Cisco Systems

Garmin Logo

Garmin

Keysight Technologies Logo

Keysight Technologies

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2 years ago
Design
2 years ago
Could you explain the operational differences between single port and multi-port SRAM/DRAM? How do you maximize memory efficiency and minimize access time?
Design Verification Engineer

Cisco Systems

Harley-Davidson Logo

Harley-Davidson

ASUS Logo

ASUS

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2 years ago
Circuits
2 years ago
Can you describe the function of a shift register and provide a circuit diagram to illustrate its operation?
Design Verification Engineer

Cisco Systems

OMRON Logo

OMRON

Canon Logo

Canon

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2 years ago
Technical
3 years ago
In your view, what is the importance of the factory in UVM?
Design Verification Engineer

Cisco Systems

Realtek Logo

Realtek

Qualcomm Logo

Qualcomm

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3 years ago
Verilog Coding
3 years ago
How would you frame an SVA in System Verilog to validate the timing order of a signal going from 0 to 1, preceding another's switch from 1 to 0?
Design Verification Engineer

Cisco Systems

Kawasaki Heavy Industries Logo

Kawasaki Heavy Industries

Philips Healthcare Logo

Philips Healthcare

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3 years ago
Technical
3 years ago
What is the significance of virtual functions in OOP, and in what ways are they different from ordinary member functions?
Design Verification Engineer

Cisco Systems

Varian Medical Systems Logo

Varian Medical Systems

Silicon Motion Logo

Silicon Motion

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3 years ago
CircuitsDesign
3 years ago
In your process of designing a circuit with adders and gates, what factors do you take into account?
Design Verification Engineer

Cisco Systems

Amgen Logo

Amgen

ASUS Logo

ASUS

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3 years ago

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*All interview questions are submitted by recent Cisco Systems Design Verification Engineer candidates, labelled and categorized by Prepfully, and then published after being verified by Design Verification Engineers at Cisco Systems.

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