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Design

2 years ago

What strategies would you employ to develop routing algorithms for a switch/router with various ports and speeds, aiming for balanced bandwidth sharing?

Design Verification Engineer

Cisco Systems

Philips

LG Electronics

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2 years ago

Design

2 years ago

What's your understanding of the workings of transceivers and arbiters? How do you ensure data is accurate and power consumption is minimal?

Design Verification Engineer

Cisco Systems

Siemens

Analog Devices

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2 years ago

Technical

2 years ago

How would you define a virtual class in SystemVerilog?

Design Verification Engineer

Cisco Systems

KTM AG

TP-Link

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2 years ago

Verilog Coding

2 years ago

Can you formulate HDL for a FSM with states IDLE, READ, and WRITE, with transitions governed by "op" and a consistent return to IDLE every 4 cycles?

Design Verification Engineer

Cisco Systems

Hitachi

Belkin

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2 years ago

Computer Architecture

2 years ago

What are the fundamental differences between a bus and a crossbar in computing systems?

Design Verification Engineer

Cisco Systems

Continental

Toshiba

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2 years ago

DesignCircuits

2 years ago

How would you go about designing a multi-bit FIFO circuit?

Design Verification Engineer

Cisco Systems

Cypress Semiconductor

Agilent Technologies

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2 years ago

Verilog Coding

2 years ago

Compose Verilog code for a detector that can identify positive and negative edges.

Design Verification Engineer

Cisco Systems

GlobalFoundries

Yokogawa Electric

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2 years ago

Technical

2 years ago

Can you explain how you would rectify a setup and hold time violation?

Design Verification Engineer

Cisco Systems

STMicroelectronics

Autodesk

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2 years ago

Design

2 years ago

In what way would you construct a 3 bit shift register using verilog RTL?

Design Verification Engineer

Cisco Systems

CRRC

Dell

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2 years ago

Technical

2 years ago

What benefits do assertions bring to our processes?

Design Verification Engineer

Cisco Systems

Skyworks Solutions

Triumph Motorcycles

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2 years ago

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^*All interview questions are submitted by recent Cisco Systems Design Verification Engineer candidates, labelled and categorized by Prepfully, and then published after being verified by Design Verification Engineers at Cisco Systems.

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