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Technical

a year ago

In UVM, what is the objection mechanism and how can one effectively finish a test?

Design Verification Engineer

Meta

GlobalFoundries

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a year ago

Circuits

a year ago

How do you configure 2:1 multiplexers to function as a NAND gate?

Design Verification Engineer

Microsoft

Beckman Coulter

GlobalFoundries

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a year ago

Technical

a year ago

In your view, how do positive and negative edge triggers in Verilog differ?

Design Verification Engineer

AIRBUS

Boston Scientific

Teradyne

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a year ago

Technical

a year ago

How extensive is your experience with Verilog in design and verification? Could you provide a project example where you used Verilog?

Design Verification Engineer

Palo Alto Networks

Apple

Cirrus Logic

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a year ago

Technical

a year ago

Could you describe the nature and purpose of a virtual class in SystemVerilog?

Design Verification Engineer

STMicroelectronics

NETGEAR

Acer

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a year ago

Technical

a year ago

Can you describe the SD Card behavioral model from your project and the challenges you encountered?

Design Verification Engineer

Amazon

General Motors

Fujitsu

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a year ago

Design

a year ago

How would you describe the importance and function of a clock tree within VLSI design systems?

Design Verification Engineer

Honeywell

AT&T

SK Hynix

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a year ago

Algorithms

a year ago

How would you code the Fibonacci series in C++?

Design Verification Engineer

Apple

Palo Alto Networks

National Instruments

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a year ago

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Amazon

Design Verification Engineer

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Behavioral

Google

Design Verification Engineer

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Behavioral

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^*All interview questions are submitted by recent Design Verification Engineer candidates, labelled and categorized by Prepfully, and then published after verification by current and ex-Design Verification Engineer employees.