Prepfully logo
  • Browse Coaches
  • Login
BetaTry Out Our New AI Mock Interviewer – Your Smartest Way to Ace Any Interview!Try Our AI Mock Interviewer
Try Now
NewRegister as a coach and get a $100 bonus on your first completed session if you're on the Prepfully Request for Coaches list.Coach $100 Bonus
Read More
LimitedEaster Deal: Heavy discounts on all Prepfully sessions.Easter Deal: Discounts
Book Now

Your AI Wingman for your next interview

The most comprehensive bank Interview Answer Review tooling available online.

Cutting-edge AI technology meets personalized feedback. Improve your interview answers with insightful guidance provided by a model trained against more than a million human-labelled interview answers.
  • Company rubrics
  • Role-level optimisations
  • Trained on 1mil+ answers
Technical
a year ago
In terms of functionality, how do module and class-based Testbenches vary?
Design Verification Engineer

LG Electronics

Ford Motor Company

IBM

Get answer reviewed by AI
a year ago
Technical
a year ago
Could you clarify the distinctions between a 'fork' and a 'join' in the context of multithreaded systems?
Design Verification Engineer

Qualcomm

Philips Healthcare

Cruise

Get answer reviewed by AI
a year ago
Verilog Coding
a year ago
Can you describe the process for implementing a programmable bitwidth 32-word 2R1W RF?
Design Verification Engineer
Audi Logo

Audi

Sumitomo Electric Logo

Sumitomo Electric

Waymo Logo

Waymo

Get answer reviewed by AI
a year ago
Technical
a year ago
How do you go about verifying the correctness of your design?
Design Verification Engineer
Oracle Logo

Oracle

Polaris Industries Logo

Polaris Industries

Siemens Logo

Siemens

Get answer reviewed by AI
a year ago
Behavioral
a year ago
Please provide a rapid rundown of your work experience.
Design Verification EngineerEmbedded Engineer
Microsoft Logo

Microsoft

Synopsys Logo

Synopsys

NEC Logo

NEC

Get answer reviewed by AI
a year ago
Technical
a year ago
How do you go about formulating a test plan for a design verification project?
Design Verification Engineer
BMW Group Logo

BMW Group

Yamaha Motor Corporation Logo

Yamaha Motor Corporation

AIRBUS Logo

AIRBUS

Get answer reviewed by AI
a year ago
Behavioral
a year ago
What challenging situation from your career do you find most memorable?
Design Verification EngineerEmbedded Engineer
Bombardier Logo

Bombardier

Thermo Fisher Scientific Logo

Thermo Fisher Scientific

Juul Labs Logo

Juul Labs

Get answer reviewed by AI
a year ago
Technical
a year ago
Can you discuss your previous experience with UVM and System Verilog?
Design Verification Engineer
Amazon Logo

Amazon

NVIDIA Logo

NVIDIA

Peloton Logo

Peloton

Get answer reviewed by AI
a year ago
Verilog Coding
a year ago
Can you formulate HDL for a FSM with states IDLE, READ, and WRITE, with transitions governed by "op" and a consistent return to IDLE every 4 cycles?
Design Verification Engineer
Mentor Graphics Logo

Mentor Graphics

NXP Semiconductors Logo

NXP Semiconductors

NVIDIA Logo

NVIDIA

Get answer reviewed by AI
a year ago
Circuits
a year ago
In a pulse generator circuit featuring a 2-input NAND gate and a series of inverters causing a propagation delay, how would the output correspond to the input timing diagram?
Design Verification Engineer
Microsoft Logo

Microsoft

Johnson Controls Logo

Johnson Controls

Lattice Semiconductor Logo

Lattice Semiconductor

Get answer reviewed by AI
a year ago

Try Free AI Interview

Amazon logo

Amazon

Design Verification Engineer

Prepare for Behavioral interview at Amazon

Behavioral
Google logo

Google

Design Verification Engineer

Prepare for Behavioral interview at Google

Behavioral
Meta logo

Meta

Design Verification Engineer

Prepare for Behavioral interview at Meta

Behavioral

Question of the week

We'll send you a weekly question to practice for:

Showing 9791 to 9800 of 32162 results

Previous978979980981982Next

*All interview questions are submitted by recent Design Verification Engineer candidates, labelled and categorized by Prepfully, and then published after verification by current and ex-Design Verification Engineer employees.

  • Company
  • FAQs
  • Contact Us
  • Become An Expert
  • Services
  • Practice Interviews
  • Interview Guides
  • Interview Questions
  • Watch Recorded Interviews
  • Gift sessions
  • AI Interview
  • Social
  • Twitter
  • Facebook
  • LinkedIn
  • YouTube
  • Legal
  • Terms & Conditions
  • Privacy Policy
  • Illustrations by Storyset

© 2025 Prepfully. All rights reserved.

Prepfully logo

Please log in to view more questions.

Not a member yet? Sign up for free.