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Technical
2 years ago
How do virtual functions function in OOP, and what sets them apart from regular member functions?
Design Verification Engineer

Meta

Varian Medical Systems

Silicon Motion

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2 years ago
Design
2 years ago
Please explain your process in designing interrupt controllers for different processors. How do you handle and sequence multiple interrupt requests?
Design Verification Engineer

Microsoft

Apple

Autodesk

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2 years ago
Computer Architecture
2 years ago
What distinguishes pipelining from parallel processing in computer architecture?
Design Verification Engineer

Silicon Motion

Intel Logo

Intel

Teradyne Logo

Teradyne

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2 years ago
Technical
2 years ago
How do you plan to test the functionality of this ALU black box? What strategies would you use to enhance its performance through superscalar or pipelining techniques?
Design Verification Engineer
LG Electronics Logo

LG Electronics

Micron Technology Logo

Micron Technology

Mentor Graphics Logo

Mentor Graphics

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2 years ago
Technical
2 years ago
What characteristics set apart a flip flop from a latch?
Design Verification Engineer
Hewlett Packard Logo

Hewlett Packard

Polaris Industries Logo

Polaris Industries

Honeywell Logo

Honeywell

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2 years ago
Algorithms
2 years ago
Can you explain why Perl might be a better choice than other scripting languages?
Design Verification Engineer
Google Logo

Google

Prysmian Group Logo

Prysmian Group

FLIR Systems Logo

FLIR Systems

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2 years ago
Circuits
2 years ago
What roles do the various phases in UVM play, and how is each phase initiated?
Design Verification Engineer

Microsoft

Apple

Palo Alto Networks Logo

Palo Alto Networks

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2 years ago
Circuits
2 years ago
Can you describe the impact on the voltages of two parallel capacitors with different charges when the connecting transistor is turned on?
Design Verification Engineer
Google Logo

Google

Beckman Coulter Logo

Beckman Coulter

Dialog Semiconductor Logo

Dialog Semiconductor

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2 years ago
Circuits
2 years ago
Can you describe the distinctions between positive and negative edge-triggered flip-flops?
Design Verification Engineer
Google Logo

Google

Xilinx Logo

Xilinx

Peloton Logo

Peloton

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2 years ago
Circuits
2 years ago
Given a pulse generator circuit with a NAND gate and staggered inputs due to inverters, how does this affect the output compared to the input timing?
Design Verification Engineer

Microsoft

Raymarine Logo

Raymarine

Lattice Semiconductor Logo

Lattice Semiconductor

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2 years ago

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Amazon

Design Verification Engineer

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Behavioral
Google logo

Google

Design Verification Engineer

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Behavioral
Meta logo

Meta

Design Verification Engineer

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Behavioral

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*All interview questions are submitted by recent Design Verification Engineer candidates, labelled and categorized by Prepfully, and then published after verification by current and ex-Design Verification Engineer employees.

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