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Circuits
10 months ago
Why are NAND gates typically chosen for D-flipflops and not NOR gates?
Design Verification Engineer

Western Digital

Rockwell Collins

Northrop Grumman

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10 months ago
Behavioral
10 months ago
How would you address the issue of a colleague frequently being late to scheduled gatherings?
Design Verification EngineerEmbedded Engineer

Western Digital

Microchip Technology Logo

Microchip Technology

Xiaomi Logo

Xiaomi

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10 months ago
Technical
10 months ago
What is your process for ensuring the accuracy of a design?
Design Verification Engineer

Western Digital

Polaris Industries Logo

Polaris Industries

Siemens Logo

Siemens

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10 months ago
Design
a year ago
Can you demonstrate your knowledge of bit manipulation with an example from your professional background?
Design Verification Engineer

Western Digital

Silicon Labs Logo

Silicon Labs

AT&T Logo

AT&T

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a year ago
Design
a year ago
How do you handle black box verification and what's your strategy for constructing a test plan?
Design Verification Engineer

Western Digital

Johnson Controls Logo

Johnson Controls

General Electric Logo

General Electric

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a year ago
Technical
a year ago
How would you characterize the verification environment for Ethernet MAC IP, including its various elements?
Design Verification Engineer

Western Digital

Apple Logo

Apple

ASML Logo

ASML

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a year ago
Behavioral
a year ago
Why do you believe you're the best fit for the Design Verification Engineer role at our company?
Design Verification Engineer

Western Digital

D-Link Logo

D-Link

Analog Devices Logo

Analog Devices

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a year ago
Design
a year ago
What assertions would you implement for a FIFO design, and what conditions would you verify for its effective operation?
Design Verification Engineer

Western Digital

Philips Logo

Philips

ON Semiconductor Logo

ON Semiconductor

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a year ago
Design
a year ago
Please detail the workings of cache memories and controllers. What methods do you employ to optimize cache performance and shorten access times?
Design Verification Engineer

Western Digital

Belkin Logo

Belkin

Aurora Logo

Aurora

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a year ago
Algorithms
a year ago
How would you design and code an LRU cache policy in C++?
Design Verification Engineer

Western Digital

Fujitsu Logo

Fujitsu

Tesla Logo

Tesla

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a year ago

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*All interview questions are submitted by recent Western Digital Design Verification Engineer candidates, labelled and categorized by Prepfully, and then published after being verified by Design Verification Engineers at Western Digital.

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