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Design
4 years ago
Could you outline how single port and multi-port SRAM/DRAM work? What is your approach to enhancing memory utilization and reducing access time?
Design Verification Engineer

Western Digital

Harley-Davidson

ASUS

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4 years ago
Design
4 years ago
Could you explain the differences between delay and slew rate in VLSI design?
Design Verification Engineer

Western Digital

Sony

Northrop Grumman

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4 years ago
Technical
4 years ago
What do you understand by setup time and hold time? How do these times get violated and what are some effective ways to reduce such violations?
Design Verification Engineer

Western Digital

Embraer Logo

Embraer

Amazon Logo

Amazon

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4 years ago
Chip Design
4 years ago
Conceptualize a sequence detector that is capable of spotting the 101 pattern in a serial bit stream.
Design Verification Engineer

Western Digital

Teradyne Logo

Teradyne

OMRON Logo

OMRON

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4 years ago
CircuitsDesign
4 years ago
What’s your plan for engineering a multi-bit FIFO circuit?
Design Verification Engineer

Western Digital

Northrop Grumman

Taiwan Semiconductor Logo

Taiwan Semiconductor

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4 years ago
Behavioral
4 years ago
What are your core competencies that align you with this role?
Design Verification EngineerEmbedded Engineer

Western Digital

Autodesk Logo

Autodesk

National Instruments Logo

National Instruments

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4 years ago
Design
4 years ago
Can you detail the role and necessity of a clock tree in the context of VLSI design?
Design Verification Engineer

Western Digital

AT&T Logo

AT&T

SK Hynix Logo

SK Hynix

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4 years ago
Verilog Coding
4 years ago
Could you draft Verilog code for detecting both positive and negative edges?
Design Verification Engineer

Western Digital

AT&T Logo

AT&T

Medtronic Logo

Medtronic

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4 years ago
Technical
4 years ago
Where is the implementation of a lock-up latch most effective?
Design Verification Engineer

Western Digital

Juul Labs Logo

Juul Labs

Lattice Semiconductor Logo

Lattice Semiconductor

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4 years ago
Verilog Coding
4 years ago
Illustrate the contrast between rand and randc in SystemVerilog, with examples for both.
Design Verification Engineer

Western Digital

STMicroelectronics Logo

STMicroelectronics

Panasonic Logo

Panasonic

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4 years ago

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*All interview questions are submitted by recent Western Digital Design Verification Engineer candidates, labelled and categorized by Prepfully, and then published after being verified by Design Verification Engineers at Western Digital.

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