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CircuitsDesign
3 years ago
Please provide a Verilog design for a routing circuit with multiple outputs and an enable signal, based on a two-bit input address.
Design Verification Engineer

Western Digital

KLA

Ducati

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3 years ago
Technical
3 years ago
How are the 'new' and 'create' methods in UVM distinct from each other?
Design Verification Engineer

Western Digital

Fujitsu

GlobalFoundries

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3 years ago
Behavioral
3 years ago
Describe a scenario where you exemplified ownership in your duties.
Design Verification EngineerEmbedded Engineer

Western Digital

Waymo Logo

Waymo

Xilinx Logo

Xilinx

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3 years ago
Technical
3 years ago
Can you elucidate on the nature of Verilog and SystemVerilog and their main differences?
Design Verification Engineer

Western Digital

Bombardier Logo

Bombardier

Oppo Logo

Oppo

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3 years ago
Verilog Coding
3 years ago
How would you design an SVA in System Verilog to verify a signal switches from 0 to 1 prior to another signal's transition from 1 to 0?
Design Verification Engineer

Western Digital

Kawasaki Heavy Industries Logo

Kawasaki Heavy Industries

Philips Healthcare Logo

Philips Healthcare

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3 years ago
Technical
3 years ago
In UVM, why is there a preference for the create method over using a new constructor?
Design Verification Engineer

Western Digital

Thales Logo

Thales

Nuvoton Technology Logo

Nuvoton Technology

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3 years ago
Design
4 years ago
How will you formulate routing algorithms for a multi-port and multi-speed switch/router to ensure fair bandwidth distribution?
Design Verification Engineer

Western Digital

Northrop Grumman Logo

Northrop Grumman

STMicroelectronics Logo

STMicroelectronics

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4 years ago
Technical
4 years ago
Why have mailboxes been selected for communication between TB components rather than queues?
Design Verification Engineer

Western Digital

Audi Logo

Audi

Seagate Technology Logo

Seagate Technology

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4 years ago
Technical
4 years ago
How would you describe the testbench you developed for a certain project?
Design Verification Engineer

Western Digital

Google Logo

Google

Juul Labs Logo

Juul Labs

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4 years ago
Technical
4 years ago
Can you define an assertion in SystemVerilog and its role in design verification?
Design Verification Engineer

Western Digital

GlobalFoundries

Rohde & Schwarz Logo

Rohde & Schwarz

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4 years ago

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*All interview questions are submitted by recent Western Digital Design Verification Engineer candidates, labelled and categorized by Prepfully, and then published after being verified by Design Verification Engineers at Western Digital.

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