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Verilog Coding
a year ago
How do you craft an SVA in System Verilog to monitor an input signal's adherence to setup and hold times?
Design Verification Engineer

Volkswagen

Mayo Clinic

Qualcomm

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a year ago
Verilog Coding
a year ago
In Verilog, how can you set a 10x9 array to zero at 0ns in an initial block?
Design Verification Engineer

Volkswagen

Beckman Coulter

Bombardier Transportation

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a year ago
Technical
a year ago
Can you outline the components of the testbench you assembled for a particular project?
Design Verification Engineer

Volkswagen

Google Logo

Google

Juul Labs Logo

Juul Labs

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a year ago
Technical
a year ago
How do you interpret an assertion in SystemVerilog, especially in the context of design verification?
Design Verification Engineer

Volkswagen

GlobalFoundries Logo

GlobalFoundries

Rohde & Schwarz Logo

Rohde & Schwarz

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a year ago
Computer Architecture
2 years ago
How do pipelining and parallel processing differ in computer architecture?
Design Verification Engineer

Volkswagen

Intel Logo

Intel

Teradyne Logo

Teradyne

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2 years ago
Circuits
2 years ago
What's the outcome on the voltages of two parallel capacitors with different charges when the transistor between them is activated?
Design Verification Engineer

Volkswagen

Dialog Semiconductor Logo

Dialog Semiconductor

Kingston Technology Logo

Kingston Technology

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2 years ago
Technical
2 years ago
How do reg, logic, and wire datatypes in System Verilog differ?
Design Verification Engineer

Volkswagen

Johnson Controls Logo

Johnson Controls

MediaTek Logo

MediaTek

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2 years ago
Technical
2 years ago
In your workflow, how do you conduct IP verification? Suppose a new IP is integrated into your design, how do you verify its functionality?
Design Verification Engineer

Volkswagen

Aurora Logo

Aurora

Sharp Logo

Sharp

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2 years ago
Behavioral
2 years ago
Share a project you've worked on that fills you with pride. What made it special?
Design Verification EngineerEmbedded Engineer

Volkswagen

HP Logo

HP

Rolls-Royce Aerospace Logo

Rolls-Royce Aerospace

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2 years ago
Circuits
2 years ago
How do you plan to assess the depth of a FIFO?
Design Verification Engineer

Volkswagen

KLA Logo

KLA

BMW Group Logo

BMW Group

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2 years ago

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