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DesignAlgorithms

a year ago

In what manner would you approach the design of a bubble sort module that works in one cycle?

Design Verification Engineer

Synopsys

Nokia

STMicroelectronics

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a year ago

Behavioral

a year ago

Discuss how you change your communication approach for maximum effectiveness.

Design Verification EngineerEmbedded Engineer

Synopsys

BAE Systems

Microchip Technology

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a year ago

Circuits

2 years ago

If restricted to write(addr, data) and read(addr, &data) APIs, how would you approach identifying a shorted internal signal in a device?

Design Verification Engineer

Synopsys

Legrand

Applied Materials

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2 years ago

Technical

2 years ago

How do you interpret the role and structure of a Testbench?

Design Verification Engineer

Synopsys

Broadcom

Philips Healthcare

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2 years ago

Technical

2 years ago

In Verilog, how do blocking assignments contrast with non-blocking ones?

Design Verification Engineer

Synopsys

Medtronic

Xilinx

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2 years ago

Circuits

2 years ago

Why are D-flipflops and similar devices usually built with NAND gates instead of NOR gates?

Design Verification Engineer

Synopsys

Rockwell Collins

Northrop Grumman

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2 years ago

Verilog Coding

2 years ago

How do you envision coding a HDL FSM with IDLE, READ, WRITE states, changing states on "op" input and returning to IDLE after 4 clock cycles?

Design Verification Engineer

Synopsys

NXP Semiconductors

NVIDIA

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2 years ago

Embedded CodingTechnical Knowledge

2 years ago

What are the key functions of a locator in the context of embedded systems?

Embedded Engineer

Synopsys

Xilinx

Valeo

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2 years ago

Circuits

2 years ago

What do the propagation delay terms C2Q, S2Q, and R2Q signify in flip-flops?

Design Verification Engineer

Synopsys

Rohde & Schwarz

Arm

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2 years ago

Design

2 years ago

Can you draft a design for a 3 bit shift register in verilog RTL?

Design Verification Engineer

Synopsys

NETGEAR

Infineon

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2 years ago

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Showing 81 to 90 of 273 results

^*All interview questions are submitted by recent Synopsys candidates, labelled and categorized by Prepfully, and then published after verification by current and ex-Synopsys employees.