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Verilog Coding
2 years ago
Could you specify the outcome for 'out' when 'a' is “1’bx”?
Design Verification Engineer

Synopsys

Eaton

Safran

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2 years ago
Technical
2 years ago
In software development, how would you go about implementing a queue?
Design Verification Engineer

Synopsys

Micron Technology Logo

Micron Technology

AIRBUS Logo

AIRBUS

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2 years ago
Behavioral
2 years ago
Share with us a community you deeply care about. How would you choose to make a contribution to it?
Embedded EngineerDesign Verification Engineer

Synopsys

Adobe Logo

Adobe

Northrop Grumman Logo

Northrop Grumman

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2 years ago
Behavioral
2 years ago
What tactics do you employ to earn the trust of your team?
Embedded EngineerDesign Verification Engineer

Synopsys

GlobalFoundries Logo

GlobalFoundries

Fujitsu Logo

Fujitsu

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2 years ago
Behavioral
2 years ago
Reflect on a time you found it challenging to meet a deadline. What actions did you take?
Design Verification Engineer

Synopsys

Aurora Logo

Aurora

Oracle Logo

Oracle

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2 years ago
Behavioral
2 years ago
Narrate an experience of successfully convincing someone about your idea. What steps did you take?
Design Verification EngineerEmbedded Engineer

Synopsys

Amgen Logo

Amgen

Novartis Logo

Novartis

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2 years ago
Verilog Coding
2 years ago
How would you script a Verilog code to initialize a 10x9 array with zeros at 0ns in an initial block?
Design Verification Engineer

Synopsys

Beckman Coulter Logo

Beckman Coulter

Bombardier Transportation Logo

Bombardier Transportation

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2 years ago
Behavioral
2 years ago
Please describe a time when you took the helm of a team. What did you learn?
Embedded EngineerDesign Verification Engineer

Synopsys

ON Semiconductor Logo

ON Semiconductor

Waymo Logo

Waymo

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2 years ago
Behavioral
2 years ago
Could you discuss the most imaginative idea you've created?
Embedded EngineerDesign Verification Engineer

Synopsys

AT&T Logo

AT&T

Medtronic Logo

Medtronic

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2 years ago
Design
2 years ago
I'd like to know how single port/multi-port SRAM/DRAM functions. How do you go about optimizing memory usage and reducing access times?
Design Verification Engineer

Synopsys

Harley-Davidson Logo

Harley-Davidson

ASUS Logo

ASUS

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2 years ago

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*All interview questions are submitted by recent Synopsys candidates, labelled and categorized by Prepfully, and then published after verification by current and ex-Synopsys employees.

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