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Chip Design
a month ago
Formulate a sequence detector that specializes in detecting the 101 pattern in serial bit streams.
Design Verification Engineer

Amazon

Microsoft

Nuro

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a month ago
Behavioral
a month ago
What recent craft conferences have you attended, and what were some significant learnings from them?
Design Verification EngineerEmbedded Engineer

Microsoft

Texas Instruments

Micron Technology

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a month ago
Technical
a month ago
How do you perceive the differences between SystemVerilog assertions and UVM assertions?
Design Verification Engineer

Microsoft

Peloton Logo

Peloton

Toshiba Logo

Toshiba

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a month ago
Technical
a month ago
Can you demonstrate the use of K-maps in reducing the complexity of a Boolean expression?
Design Verification Engineer
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Cypress Semiconductor

Agilent Technologies Logo

Agilent Technologies

Lam Research Logo

Lam Research

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a month ago
Design
a month ago
In the context of AXI or similar protocols, how do master and slave agents function on a shared bus and what strategies would you use to ensure data integrity and prevent bus conflicts?
Design Verification Engineer
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Lockheed Martin

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Aurora

Teradyne Logo

Teradyne

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a month ago
Design
a month ago
Can you describe the concept of parasitic resistance and its relevance in VLSI design?
Design Verification Engineer

Microsoft

Dell Technologies Logo

Dell Technologies

NXP Semiconductors Logo

NXP Semiconductors

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a month ago
Algorithms
a month ago
What makes Perl advantageous when compared to alternative scripting languages?
Design Verification Engineer
HP Logo

HP

Prysmian Group Logo

Prysmian Group

FLIR Systems Logo

FLIR Systems

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a month ago
Design
a month ago
Can you clarify the workings of transceivers and arbiters? What are your approaches to data integrity and power saving?
Design Verification Engineer
Palo Alto Networks Logo

Palo Alto Networks

Microsoft

Amazon

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a month ago
Verilog Coding
a month ago
Can you detail the process of setting up an SVA in System Verilog to ensure a signal's rise from 0 to 1 before another's descent from 1 to 0?
Design Verification Engineer
D-Link Logo

D-Link

Kawasaki Heavy Industries Logo

Kawasaki Heavy Industries

Philips Healthcare Logo

Philips Healthcare

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a month ago
Behavioral
a month ago
What steps would you take if a peer consistently arrives late to a recurring meeting?
Design Verification EngineerEmbedded Engineer
Google Logo

Google

Apple Logo

Apple

ZTE Logo

ZTE

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a month ago

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Amazon

Design Verification Engineer

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Google

Design Verification Engineer

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Behavioral
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Meta

Design Verification Engineer

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Behavioral

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