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Behavioral
a month ago
Share an experience where you found it hard to meet a deadline. What steps did you take?
Design Verification Engineer

Texas Instruments

Aurora

Oracle

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a month ago
Behavioral
a month ago
Could you detail a specific conflict situation and your approach to resolving it?
Design Verification EngineerEmbedded Engineer

Bosch

STMicroelectronics

Northrop Grumman

During one of our verification projects, we faced a challenge in defining the right test strategy for a new design block. I strongly advocated for merging an existing, previously verified block into a shared verification environment, believing it would improve efficiency and catch bugs with minimal effort. However, my teammate strongly advocated for a standalone block-level verification, arguing it would provide more deterministic coverage. This disagreement led to delays in testbench development and friction between us.

Recognizing the need for alignment, I initiated a structured discussion where we both presented our viewpoints with supporting data. I focused on ensuring we evaluated the trade-offs objectively rather than debating which approach was superior. After evaluating the pros and cons, I proposed a hybrid approach: conducting initial verification within the combined testbench for faster validation while simultaneously estimating the effort required for a standalone testbench. Once we mapped out our plans, we found that my approach led to a faster testbench setup, while his plan had overlaps in checker development. Recognizing this, we aligned on using the existing testbench while developing only the necessary new checkers. Later, we proposed building a dedicated block-level testbench to further improve coverage and verification confidence. This approach was well received by architects, designers, and management, as it balanced efficiency and thorough testing. It was a proud moment for me because it demonstrated the power of collaborative problem-solving, data-driven decision-making, and adaptability. This experience reinforced my belief that fostering open discussions, considering multiple perspectives, and focusing on practical solutions leads to stronger team synergy and better project outcomes.

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a month ago
Design
a month ago
How would you describe the importance and function of a clock tree within VLSI design systems?
Design Verification Engineer
Ford Motor Company Logo

Ford Motor Company

AT&T Logo

AT&T

SK Hynix Logo

SK Hynix

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a month ago
Technical
a month ago
Can you identify the applications for a lock-up latch?
Design Verification Engineer
Google Logo

Google

Microsoft Logo

Microsoft

Yamaha Motor Corporation Logo

Yamaha Motor Corporation

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a month ago
Technical
a month ago
Can you demonstrate the use of K-maps in reducing the complexity of a Boolean expression?
Design Verification Engineer
General Motors Logo

General Motors

Agilent Technologies Logo

Agilent Technologies

Lam Research Logo

Lam Research

The k-map helps in deriving the simplified expressions for the given set of minterms. It basically solves the expressions by making group of minterms in the order of maximum combinations, for a 2 variable the maximum combination is 4 followed by 2, and finally 1.

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a month ago
Technical
a month ago
What unique aspects do module-based and class-based Testbenches have?
Design Verification Engineer
Agilent Technologies Logo

Agilent Technologies

Ford Motor Company Logo

Ford Motor Company

IBM Logo

IBM

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a month ago
Behavioral
a month ago
Narrate your involvement in a project that you feel was a major success. Why do you think so?
Design Verification EngineerEmbedded Engineer
Google Logo

Google

Zoox Logo

Zoox

HP Logo

HP

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a month ago
AlgorithmsDesign
a month ago
In what manner would you approach the design of a bubble sort module that works in one cycle?
Design Verification Engineer
Apple Logo

Apple

Google Logo

Google

Sony Logo

Sony

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a month ago
Behavioral
a month ago
What do you consider to be your greatest professional success?
Design Verification EngineerEmbedded Engineer
Abbott Laboratories Logo

Abbott Laboratories

Comau Robotics Logo

Comau Robotics

Atlas Copco Logo

Atlas Copco

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a month ago
Circuits
a month ago
Using the write(addr, data) and read(addr, &data) APIs only, can you explain your method to identify a shorted internal signal in a device?
Design Verification Engineer
Google Logo

Google

Legrand Logo

Legrand

Applied Materials Logo

Applied Materials

A short circuit in an internal signal implies that this signal is electrically connected to another signal, possibly VCC or GND. This will cause unexpected behavior when either of the shorted signals is driven.

Algorithm

  1. Initialization
    Gather information about the device:Addressable memory range.
    Data width at each address.
    Any known 'safe' addresses (e.g., read-only registers that won't affect device operation when written to).
    If no safe addresses are known, start with the highest address and work downwards to minimize the risk of disrupting critical functionality early in the process.
  2. Write-Read-Verify Loop
    For each address addr in the memory range:read(addr, &original_data): Read the original data at the address.
    new_data = ~original_data: Invert the original data.
    write(addr, new_data): Write the inverted data to the address.
    read(addr, &read_back_data): Read back the data from the same address.

    Compare:If read_back_data == new_data, the write was successful, move to the next address.

    If read_back_data != new_data:write(addr, original_data): Restore the original data to minimize disruption
    Potential Short: There's a potential short circuit involving a signal affected by writing to this address.

    Further Investigation:Try writing different patterns to the address and observe the read-back data.
    If the read-back data consistently reflects an unexpected pattern or is stuck at a particular value regardless of the written data, it strengthens the possibility of a short circuit.
    Log the address and the observed behavior for further analysis.
  3. Analysis
  • Correlate the addresses where unexpected behavior was observed.
  • Look for patterns:Are the problematic addresses contiguous or spread out?
    Do specific bit patterns in the read-back data suggest a connection to VCC, GND, or another signal?
  • Use your understanding of the device's functionality (even if limited) to hypothesize which internal signals might be shorted based on the affected addresses.

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a month ago

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Design Verification Engineer

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Meta

Design Verification Engineer

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