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Computer Architecture
2 years ago
Can you contrast pipelining with parallel processing in the context of computer architecture?
Design Verification Engineer

Microsoft

Intel

Teradyne

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2 years ago
Circuits
2 years ago
Explain the dissimilarities between a latch and a flip flop, and include an example for better understanding.
Design Verification Engineer

NetApp

Northrop Grumman

Boeing

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2 years ago
Technical
2 years ago
What separates the get_next_item() method from the get() method in UVM's driver class?
Design Verification Engineer
Meta Logo

Meta

NVIDIA Logo

NVIDIA

ABB Logo

ABB

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2 years ago
Technical
2 years ago
How would you describe a Testbench in your own words?
Design Verification Engineer
Schneider Electric Logo

Schneider Electric

Broadcom Logo

Broadcom

Philips Healthcare Logo

Philips Healthcare

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2 years ago
Technical
2 years ago
How does a single-channel DMA controller function? And in what way does it handle multiple channels and peripheral agents concurrently?
Design Verification Engineer
Autodesk Logo

Autodesk

Sony Logo

Sony

Marvell Logo

Marvell

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2 years ago
Design
2 years ago
Could you illustrate the process of constructing a 3 bit shift register in verilog RTL?
Design Verification Engineer
Palo Alto Networks Logo

Palo Alto Networks

Bombardier Transportation Logo

Bombardier Transportation

NETGEAR Logo

NETGEAR

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2 years ago
CircuitsDesign
2 years ago
What's your methodology for designing a circuit with adders and gates, and what are key considerations?
Design Verification Engineer
Amazon Logo

Amazon

Bombardier Logo

Bombardier

Amgen Logo

Amgen

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2 years ago
Technical
2 years ago
How do you describe the modulus of a counter and its application in a decade counter?
Design Verification Engineer

Microsoft

Vivo Logo

Vivo

Qualcomm Logo

Qualcomm

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2 years ago
Behavioral
2 years ago
What unique skills do you have that make you a suitable candidate?
Design Verification EngineerEmbedded Engineer

Microsoft

Sumitomo Electric Logo

Sumitomo Electric

Autodesk Logo

Autodesk

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2 years ago
Design
2 years ago
Can you create a 3 bit shift register using verilog RTL?
Design Verification Engineer
Palo Alto Networks Logo

Palo Alto Networks

Lockheed Martin Logo

Lockheed Martin

NETGEAR Logo

NETGEAR

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2 years ago

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Amazon

Design Verification Engineer

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Google

Design Verification Engineer

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Behavioral
Meta logo

Meta

Design Verification Engineer

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Behavioral

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*All interview questions are submitted by recent Design Verification Engineer candidates, labelled and categorized by Prepfully, and then published after verification by current and ex-Design Verification Engineer employees.

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