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Technical
2 years ago
What approach do you take to ensure the design's correctness?
Design Verification Engineer

Samsung

Polaris Industries

Siemens

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2 years ago
Technical
2 years ago
In what way do you tackle setup and hold time violations?
Design Verification Engineer

Amazon

NVIDIA

Yamaha Motor Corporation

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2 years ago
Technical
2 years ago
In software development, how would you go about implementing a queue?
Design Verification Engineer
LG Electronics Logo

LG Electronics

Micron Technology Logo

Micron Technology

AIRBUS Logo

AIRBUS

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2 years ago
Design
2 years ago
In what order do the stages in RTL design flow occur?
Design Verification Engineer
Microsoft Logo

Microsoft

Northrop Grumman Logo

Northrop Grumman

Hitachi Logo

Hitachi

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2 years ago
Technical
2 years ago
In your view, why are assertions critical in the verification process?
Design Verification Engineer

Amazon

Google Logo

Google

HP Logo

HP

Assertions helps with figuring out the illegal scenarios quicker than doing waveform or display statement debugs. Properties can be useful and can be used in both assertion and coverage.

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2 years ago
Behavioral
2 years ago
Give an example of a project that you are immensely proud of. What factors contribute to this sentiment?
Design Verification EngineerEmbedded Engineer
Google Logo

Google

Aurora Logo

Aurora

HP Logo

HP

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2 years ago
Chip Design
2 years ago
What's your strategy for developing a D flip-flop using a multiplexer?
Design Verification Engineer
Google Logo

Google

Philips Healthcare Logo

Philips Healthcare

Novartis Logo

Novartis

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2 years ago
CircuitsDesign
2 years ago
What principles guide your design of a circuit using adders and gates, and what do you prioritize?
Design Verification Engineer

Amazon

Canon Logo

Canon

Amgen Logo

Amgen

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2 years ago
Circuits
2 years ago
How is the output of a pulse generator with a 2-input NAND gate and input delays from inverters influenced by the input timing diagram?
Design Verification Engineer
Microsoft Logo

Microsoft

Analog Devices Logo

Analog Devices

Lattice Semiconductor Logo

Lattice Semiconductor

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2 years ago
Verilog Coding
2 years ago
Could you list and explain the various ways to create delays in Verilog, using examples?
Design Verification Engineer
Pratt & Whitney Logo

Pratt & Whitney

STMicroelectronics Logo

STMicroelectronics

Hewlett Packard Logo

Hewlett Packard

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2 years ago

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Amazon logo

Amazon

Design Verification Engineer

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Behavioral
Google logo

Google

Design Verification Engineer

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Behavioral
Meta logo

Meta

Design Verification Engineer

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Behavioral

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*All interview questions are submitted by recent Design Verification Engineer candidates, labelled and categorized by Prepfully, and then published after verification by current and ex-Design Verification Engineer employees.

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