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Circuits

2 years ago

How can you construct a NAND gate using exclusively 2:1 multiplexers?

Design Verification Engineer

Microsoft

AMD

GlobalFoundries

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2 years ago

Technical

2 years ago

If you receive a bug report from the verification team, what steps would you take to address it?

Design Verification Engineer

Apple

Samsung Electronics

Cirrus Logic

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2 years ago

Design

2 years ago

Can you detail the function of single and multi-port SRAM/DRAM? What strategies do you use to enhance memory usage and access speed?

Design Verification Engineer

ASML

Harley-Davidson

ASUS

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2 years ago

Technical

2 years ago

In verification, how do formal techniques differ from simulation-based approaches?

Design Verification Engineer

Nuro

LG Electronics

Infineon

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2 years ago

Technical

2 years ago

How do code coverage and functional coverage differ?

Design Verification Engineer

Palo Alto Networks

Amazon

Siemens

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2 years ago

Technical

2 years ago

What methods do you employ to resolve setup and hold time violations?

Design Verification Engineer

Amazon

Broadcom

Yamaha Motor Corporation

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2 years ago

Technical

2 years ago

Could you describe the significance of the factory in UVM?

Design Verification Engineer

Meta

Palo Alto Networks

Becton Dickinson

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2 years ago

Technical

2 years ago

Could you describe your experience working with UVM and System Verilog?

Design Verification Engineer

Amazon

Waymo

Peloton

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2 years ago

Design

2 years ago

Can you identify common violations in this field and your strategies for avoiding them?

Design Verification Engineer

Lenovo

Mentor Graphics

Sharp

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2 years ago

Circuits

2 years ago

Can you determine the output frequency of a JK flip-flop given J=K=0 and a 10MHz clock input?

Design Verification Engineer

Applied Materials

Western Digital

Alstom

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2 years ago

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Amazon

Design Verification Engineer

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Behavioral

Google

Design Verification Engineer

Prepare for Behavioral interview at Google

Behavioral

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^*All interview questions are submitted by recent Design Verification Engineer candidates, labelled and categorized by Prepfully, and then published after verification by current and ex-Design Verification Engineer employees.