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Verilog Coding
2 years ago
Craft Verilog code to create a positive/negative edge detector.
Design Verification Engineer

Amgen

AT&T

Medtronic

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2 years ago
Technical
2 years ago
What's the importance of using assertions?
Design Verification Engineer

Garmin

Fujikura

Agilent Technologies

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2 years ago
Circuits
2 years ago
What's the distinction between combinational and sequential circuits?
Design Verification Engineer
Microsoft Logo

Microsoft

Samsung Electronics Logo

Samsung Electronics

Blue Origin Logo

Blue Origin

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2 years ago
Technical
2 years ago
What is your explanation of the working mechanism of CAM?
Design Verification Engineer
Google Logo

Google

Lockheed Martin Logo

Lockheed Martin

Bombardier Logo

Bombardier

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2 years ago
Verilog Coding
2 years ago
In System Verilog, how would you establish an assertion to maintain setup and hold time requirements for an input signal?
Design Verification Engineer
Bosch Logo

Bosch

Mayo Clinic Logo

Mayo Clinic

Qualcomm Logo

Qualcomm

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2 years ago
Behavioral
2 years ago
Describe a scenario where you exemplified ownership in your duties.
Design Verification EngineerEmbedded Engineer
Kingston Technology Logo

Kingston Technology

Waymo Logo

Waymo

Xilinx Logo

Xilinx

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2 years ago
Technical
2 years ago
What does modulus signify in a counter, and what is the modulus of a decade counter?
Design Verification Engineer
Microsoft Logo

Microsoft

D-Link Logo

D-Link

Qualcomm Logo

Qualcomm

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2 years ago
Algorithms
2 years ago
How would you go about generating two separate arrays, both 10 elements long, with no overlap?
Design Verification Engineer
Google Logo

Google

Cirrus Logic Logo

Cirrus Logic

Autodesk Logo

Autodesk

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2 years ago
Circuits
2 years ago
How would you depict the truth table for a NAND gate's functionality?
Design Verification Engineer
Amazon Logo

Amazon

Xilinx Logo

Xilinx

Sumitomo Electric Logo

Sumitomo Electric

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2 years ago
Verilog Coding
2 years ago
How would you design an SVA in System Verilog to prohibit memory read/write actions during a power-on-reset cycle?
Design Verification Engineer
Apple Logo

Apple

Google Logo

Google

Yamaha Motor Corporation Logo

Yamaha Motor Corporation

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2 years ago

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Amazon logo

Amazon

Design Verification Engineer

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Behavioral
Google logo

Google

Design Verification Engineer

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Behavioral
Meta logo

Meta

Design Verification Engineer

Prepare for Behavioral interview at Meta

Behavioral

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*All interview questions are submitted by recent Design Verification Engineer candidates, labelled and categorized by Prepfully, and then published after verification by current and ex-Design Verification Engineer employees.

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