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Technical
2 years ago
Please explain the contrast between the get_next_item() and get() methods in the UVM driver class.
Design Verification Engineer

Marvell

ABB

Dell

get_next_item is used when communicating with the sequence. it unblocks the start_item(req) in the sequence. 

get is used for communication with other components that are connected with the driver via tlm fifo port

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2 years ago
Design
2 years ago
What's your interpretation of the synthesis flow in the context of VLSI design?
Design Verification Engineer

Marvell

Synopsys

Bombardier

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2 years ago
Circuits
2 years ago
What role does a shift register play, and how is it operated, as shown in an accompanying circuit diagram?
Design Verification Engineer

Marvell

OMRON Logo

OMRON

Canon Logo

Canon

nand gate truth table 

a  b  y 

0  0  1

0  1  0

1  0  0

1  1  0

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2 years ago
Technical
2 years ago
What distinct types of timing violations are possible in RTL designs?
Design Verification Engineer

Marvell

Qualcomm Logo

Qualcomm

Acer Logo

Acer

timing violations like propagation delay, input synchronicsation and output synchronisation

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2 years ago
Design
2 years ago
How do you approach identifying and improving the critical path in digital design?
Design Verification Engineer

Marvell

Bombardier

Silicon Labs Logo

Silicon Labs

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2 years ago
Technical
2 years ago
Why is UVM considered advantageous in the realm of design verification?
Design Verification Engineer

Marvell

Xilinx Logo

Xilinx

Microsoft Logo

Microsoft

1. Reusability

2. Maintainability

3. Standard methodology makes it easier to understand the data flow for new members

4. Built-in code helps to do things in a standard way and also avoids minor mistakes

5. Scalability increases

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2 years ago
Technical
2 years ago
What are register tables and how do they fit into the design of embedded systems?
Design Verification Engineer

Marvell

Bosch Logo

Bosch

Verizon Logo

Verizon

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2 years ago
Behavioral
2 years ago
Discuss a time when you encountered a substantial setback and what you took away from it.
Design Verification EngineerEmbedded Engineer

Marvell

AT&T Logo

AT&T

Apple Logo

Apple

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2 years ago
Technical
2 years ago
What techniques would you use to overcome setup and hold time violations?
Design Verification Engineer

Marvell

Yamaha Motor Corporation Logo

Yamaha Motor Corporation

Pratt & Whitney Logo

Pratt & Whitney

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2 years ago
Technical
2 years ago
Can you explain the workings of a single-channel DMA controller? Also, how does it manage multiple parallel channels and peripherals?
Design Verification Engineer

Marvell

Sony Logo

Sony

KTM AG Logo

KTM AG

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2 years ago

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