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Algorithms
2 years ago
Please describe a method to construct two arrays, each 10 items long, ensuring all elements are distinct.
Design Verification Engineer
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Eaton

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Autodesk

TP-Link Logo

TP-Link

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2 years ago
Verilog Coding
2 years ago
Formulate assertions to pinpoint numbers representing powers of 2.
Design Verification Engineer
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Eaton

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IBM

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Peloton

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2 years ago
Technical
2 years ago
Please explain the contrast between the get_next_item() and get() methods in the UVM driver class.
Design Verification Engineer
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Eaton

ABB Logo

ABB

Dell Logo

Dell

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2 years ago
Design
2 years ago
What separates a monitor from a scoreboard in the UVM environment?
Design Verification Engineer
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Eaton

Renesas Electronics Logo

Renesas Electronics

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ASUS

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2 years ago
Behavioral
2 years ago
How do you approach the challenge of establishing trust within a team?
Design Verification EngineerEmbedded Engineer
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Eaton

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GlobalFoundries

Fujitsu Logo

Fujitsu

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2 years ago
Technical
2 years ago
In Verilog, how do blocking assignments contrast with non-blocking ones?
Design Verification Engineer
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Eaton

Medtronic Logo

Medtronic

Xilinx Logo

Xilinx

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2 years ago
Verilog Coding
2 years ago
How would you script a constraint to yield 4 unique variables?
Design Verification Engineer
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Eaton

SK Hynix Logo

SK Hynix

Sumitomo Electric Logo

Sumitomo Electric

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2 years ago
Algorithms
2 years ago
How would you go about confirming whether a given string is a palindrome?
Design Verification Engineer
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Eaton

Thales Logo

Thales

Huawei Logo

Huawei

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2 years ago
CircuitsDesign
2 years ago
How would you go about designing a multi-bit FIFO circuit?
Design Verification Engineer
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Eaton

Northrop Grumman Logo

Northrop Grumman

Taiwan Semiconductor Logo

Taiwan Semiconductor

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2 years ago
Technical
2 years ago
What are the major contrasting points between RISC and CISC?
Design Verification Engineer
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Eaton

SpaceX Logo

SpaceX

TP-Link Logo

TP-Link

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2 years ago

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