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Embedded CodingTechnical Knowledge
a year ago
How does a locator contribute to the functionality of embedded systems?
Embedded Engineer
STMicroelectronics Logo

STMicroelectronics

Cadence Design Systems Logo

Cadence Design Systems

OMRON Logo

OMRON

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a year ago
Technical
a year ago
Could you describe your process for remedying setup and hold time violations?
Design Verification Engineer
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STMicroelectronics

Autodesk Logo

Autodesk

Novartis Logo

Novartis

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a year ago
Technical
a year ago
Please provide a detailed explanation of what a Testbench is.
Design Verification Engineer
STMicroelectronics Logo

STMicroelectronics

ASUS Logo

ASUS

NVIDIA Logo

NVIDIA

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a year ago
Circuits
a year ago
What are the meanings of C2Q, S2Q, and R2Q in the context of flip-flop propagation delays?
Design Verification Engineer
STMicroelectronics Logo

STMicroelectronics

GlobalFoundries Logo

GlobalFoundries

Bombardier Transportation Logo

Bombardier Transportation

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a year ago
Design
a year ago
Describe the roles of master and slave agents in a shared bus environment using protocols like AXI, and your approach to ensuring data integrity and preventing bus contention.
Design Verification Engineer
STMicroelectronics Logo

STMicroelectronics

Hitachi Logo

Hitachi

Dell Technologies Logo

Dell Technologies

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a year ago
Circuits
a year ago
What are the key phases in UVM, and how are they triggered?
Design Verification Engineer
STMicroelectronics Logo

STMicroelectronics

Cadence Design Systems Logo

Cadence Design Systems

ASML Logo

ASML

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a year ago
Technical
a year ago
How are the 'new' and 'create' methods in UVM distinct from each other?
Design Verification Engineer
STMicroelectronics Logo

STMicroelectronics

Raytheon Logo

Raytheon

Raymarine Logo

Raymarine

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a year ago
Technical
a year ago
Could you describe the nature and purpose of a virtual class in SystemVerilog?
Design Verification Engineer
STMicroelectronics Logo

STMicroelectronics

KTM AG Logo

KTM AG

TP-Link Logo

TP-Link

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a year ago
Technical
a year ago
Could you explain the different timing violations that might occur in RTL designs?
Design Verification Engineer
STMicroelectronics Logo

STMicroelectronics

GlobalFoundries Logo

GlobalFoundries

Yokogawa Electric Logo

Yokogawa Electric

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a year ago
Embedded Coding
a year ago
Can you identify and elaborate on any bitwise operators you've used?
Embedded Engineer
STMicroelectronics Logo

STMicroelectronics

Broadcom Logo

Broadcom

ABB Logo

ABB

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a year ago

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*All interview questions are submitted by recent STMicroelectronics candidates, labelled and categorized by Prepfully, and then published after verification by current and ex-STMicroelectronics employees.

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