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Behavioral
2 years ago
Share a conflict situation you've experienced and how you addressed it.
Design Verification EngineerEmbedded Engineer
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STMicroelectronics

Northrop Grumman Logo

Northrop Grumman

National Instruments Logo

National Instruments

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2 years ago
Verilog Coding
2 years ago
How would you frame an SVA in System Verilog to validate the timing order of a signal going from 0 to 1, preceding another's switch from 1 to 0?
Design Verification Engineer
STMicroelectronics Logo

STMicroelectronics

Kawasaki Heavy Industries Logo

Kawasaki Heavy Industries

Philips Healthcare Logo

Philips Healthcare

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2 years ago
Behavioral
2 years ago
Explain how you once assisted a colleague in a task that wasn't your responsibility. How effective were you?
Design Verification EngineerEmbedded Engineer
STMicroelectronics Logo

STMicroelectronics

Agilent Technologies Logo

Agilent Technologies

Raymarine Logo

Raymarine

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2 years ago
Verilog Coding
2 years ago
How do you intend to implement a module that calculates the scalar product of vectors A and B?
Design Verification Engineer
STMicroelectronics Logo

STMicroelectronics

Bombardier Logo

Bombardier

Apple Logo

Apple

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2 years ago
Embedded Coding
2 years ago
In C, how would you construct a shared memory buffer to facilitate communication between a producer and a consumer?
Embedded Engineer
STMicroelectronics Logo

STMicroelectronics

Kingston Technology Logo

Kingston Technology

Denso Logo

Denso

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2 years ago
Behavioral
2 years ago
Can you elaborate on a situation where your decision was not well-liked?
Embedded EngineerDesign Verification Engineer
STMicroelectronics Logo

STMicroelectronics

Philips Healthcare Logo

Philips Healthcare

NetApp Logo

NetApp

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2 years ago
Design
2 years ago
In what ways does a custom cell design vary from a standard cell design?
Design Verification Engineer
STMicroelectronics Logo

STMicroelectronics

Tesla Logo

Tesla

Bosch Logo

Bosch

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2 years ago
Behavioral
2 years ago
How would you manage a situation where a fellow employee is consistently tardy to meetings?
Embedded EngineerDesign Verification Engineer
STMicroelectronics Logo

STMicroelectronics

Microchip Technology Logo

Microchip Technology

Xiaomi Logo

Xiaomi

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2 years ago
Design
2 years ago
Can you expound on the concept of a clock tree and its criticality in VLSI design?
Design Verification Engineer
STMicroelectronics Logo

STMicroelectronics

AT&T Logo

AT&T

SK Hynix Logo

SK Hynix

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2 years ago
Chip Design
2 years ago
Devise a sequence detector for identifying the 101 sequence in a serial bit stream.
Design Verification Engineer
STMicroelectronics Logo

STMicroelectronics

Teradyne Logo

Teradyne

OMRON Logo

OMRON

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2 years ago

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Product Strategy
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STMicroelectronics

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