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Technical
4 years ago
Could you explain the differences among reg, logic, and wire datatypes in System Verilog?
Design Verification Engineer

Siemens

Johnson Controls

MediaTek

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4 years ago
Behavioral
4 years ago
Is this {role} role a good fit for your qualifications?
Frontend Engineer

Siemens

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4 years ago
Behavioral
4 years ago
Explain a moment where you had to take charge of a team.
Embedded EngineerDesign Verification Engineer

Siemens

Crestron Logo

Crestron

Sharp Logo

Sharp

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4 years ago
Behavioral
4 years ago
If you were forced to make a quick decision, tell me about it.
Frontend EngineerProgram ManagerFull Stack Software EngineerData Scientist

Siemens

MasterClass Logo

MasterClass

Marketo Logo

Marketo

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4 years ago
Circuits
4 years ago
How do combinational circuits differ from sequential circuits?
Design Verification Engineer

Siemens

Blue Origin Logo

Blue Origin

Xiaomi Logo

Xiaomi

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4 years ago
People Management
4 years ago
What steps do you take to integrate new hires into your team and ensure their success?
Data Science ManagerEngineering ManagerData Engineering ManagerML Engineering Manager

Siemens

Miro Logo

Miro

Scribd Logo

Scribd

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4 years ago
Behavioral
4 years ago
Tell me about a situation where you faced a setback, and how you handled it.
UX ResearcherProduct ManagerBackend EngineerTechnical Program Manager

Siemens

JoyTunes Logo

JoyTunes

N26 Logo

N26

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4 years ago
Coding
4 years ago
Can you demonstrate a simple tool for string reversal?
Machine Learning EngineerData Scientist

Siemens

Skyscanner Logo

Skyscanner

StubHub Logo

StubHub

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4 years ago
Behavioral
4 years ago
What approaches do you use to address conflicts between two teams who are both failing to deliver a feature?
Program ManagerTechnical Program Manager

Siemens

Monzo Logo

Monzo

Lyft Logo

Lyft

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4 years ago
Technical
4 years ago
Can you compare the get_next_item() and get() methods in the UVM driver class?
Design Verification Engineer

Siemens

ABB Logo

ABB

Dell Logo

Dell

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4 years ago

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