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Technical
a year ago
Can you discuss the mechanisms of cache coherence protocols?
Design Verification Engineer

Apple

Triumph Motorcycles

Cruise

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a year ago
Circuits
a year ago
When a transistor connecting two parallel capacitors with varying charge voltages is activated, what effect does it have on the voltages?
Design Verification Engineer

Google

Amgen

Dialog Semiconductor

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a year ago
Circuits
a year ago
What frequency can be expected at the output of a JK flip-flop with J=K=0 and a clock frequency of 10MHz?
Design Verification Engineer
Raytheon Logo

Raytheon

Western Digital Logo

Western Digital

Alstom Logo

Alstom

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a year ago
Technical
a year ago
Can you explain the advantages of using create method instead of a new constructor in UVM?
Design Verification Engineer
Palo Alto Networks Logo

Palo Alto Networks

Google

Boston Scientific Logo

Boston Scientific

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a year ago
Behavioral
a year ago
Recall a situation where you assisted a co-worker in an unfamiliar area. How did you manage?
Design Verification EngineerEmbedded Engineer

Google

Amazon Logo

Amazon

Microsoft Logo

Microsoft

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a year ago
Technical
a year ago
How is the interaction between a UVM agent and a UVM sequencer structured?
Design Verification Engineer
Audi Logo

Audi

Microchip Technology Logo

Microchip Technology

Arm Logo

Arm

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a year ago
Behavioral
a year ago
Recall a situation where you had to deal with critical feedback. How did you respond?
Design Verification EngineerEmbedded Engineer
Nokia Logo

Nokia

Canon Logo

Canon

Cisco Logo

Cisco

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a year ago
Behavioral
a year ago
Describe an occasion where you persuaded someone to accept your idea. What approach did you use?
Design Verification EngineerEmbedded Engineer
Meta Logo

Meta

Microsoft Logo

Microsoft

Apple

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a year ago
Design
a year ago
How do you intend to design routing algorithms for a switch/router with multiple ports and speeds, ensuring equitable bandwidth sharing?
Design Verification Engineer
Amazon Logo

Amazon

Bosch Logo

Bosch

Northrop Grumman Logo

Northrop Grumman

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a year ago
Technical
a year ago
Have you previously engaged in projects involving UVM and System Verilog?
Design Verification Engineer
Amazon Logo

Amazon

Amgen

Peloton Logo

Peloton

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a year ago

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Amazon logo

Amazon

Design Verification Engineer

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Behavioral
Google logo

Google

Design Verification Engineer

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Behavioral
Meta logo

Meta

Design Verification Engineer

Prepare for Behavioral interview at Meta

Behavioral

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*All interview questions are submitted by recent Design Verification Engineer candidates, labelled and categorized by Prepfully, and then published after verification by current and ex-Design Verification Engineer employees.

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