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Circuits
a month ago
With a 10MHz square wave as the clock and J=K=0, what output frequency does a JK flip-flop produce?
Design Verification Engineer

Toshiba

Western Digital

Alstom

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a month ago
Design
a month ago
Could you outline how single port and multi-port SRAM/DRAM work? What is your approach to enhancing memory utilization and reducing access time?
Design Verification Engineer

Autodesk

Harley-Davidson

ASUS

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a month ago
Design
a month ago
How would you describe the importance and function of a clock tree within VLSI design systems?
Design Verification Engineer
Prysmian Group Logo

Prysmian Group

AT&T Logo

AT&T

SK Hynix Logo

SK Hynix

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a month ago
Technical
a month ago
Could you explain the UVM RAL model and its necessity?
Design Verification Engineer
Apple Logo

Apple

NVIDIA Logo

NVIDIA

Sumitomo Electric Logo

Sumitomo Electric

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a month ago
Behavioral
a month ago
Is there a particular instance where you had to confront and manage adverse feedback?
Design Verification EngineerEmbedded Engineer
Garmin Logo

Garmin

AT&T Logo

AT&T

Magneti Marelli Logo

Magneti Marelli

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a month ago
Verilog Coding
a month ago
Please provide a Verilog code sample that initializes a 10x9 array to 0 at 0ns within an initial block.
Design Verification Engineer
Silicon Labs Logo

Silicon Labs

Beckman Coulter Logo

Beckman Coulter

Bombardier Transportation Logo

Bombardier Transportation

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a month ago
Design
a month ago
Can you outline the various adders found in VLSI design? How do you enhance these adders for different application needs?
Design Verification Engineer
Amazon Logo

Amazon

Taiwan Semiconductor Logo

Taiwan Semiconductor

National Instruments Logo

National Instruments

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a month ago
Technical
a month ago
In UVM, what is the objection mechanism and how can one effectively finish a test?
Design Verification Engineer
Meta Logo

Meta

Juniper Networks Logo

Juniper Networks

Bosch Logo

Bosch

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a month ago
Circuits
a month ago
What's the outcome on the voltages of two parallel capacitors with different charges when the transistor between them is activated?
Design Verification Engineer
Google Logo

Google

Teradyne Logo

Teradyne

Dialog Semiconductor Logo

Dialog Semiconductor

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a month ago
Verilog Coding
a month ago
What is your strategy for implementing a binary to thermometer decoder circuit in Verilog?
Design Verification Engineer
Trimble Logo

Trimble

Bosch Logo

Bosch

Fujikura Logo

Fujikura

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a month ago

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Amazon

Design Verification Engineer

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Google

Design Verification Engineer

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Behavioral
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Meta

Design Verification Engineer

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Behavioral

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*All interview questions are submitted by recent Design Verification Engineer candidates, labelled and categorized by Prepfully, and then published after verification by current and ex-Design Verification Engineer employees.

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