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Technical

3 years ago

What was the behavior of the SD Card model in your project, and what were the development challenges?

Design Verification Engineer

Oppo

Fujitsu

Novartis

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3 years ago

Verilog Coding

3 years ago

What methodology would you apply to construct a 32-word 2R1W register file with programmable bitwidth?

Design Verification Engineer

Oppo

Sumitomo Electric

Waymo

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3 years ago

Circuits

3 years ago

How are propagation delays C2Q, S2Q, and R2Q defined in the context of flip-flops?

Design Verification Engineer

Oppo

Rohde & Schwarz

Arm

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3 years ago

Technical

3 years ago

Can you share your process for debugging in situations with a high volume of bugs?

Design Verification Engineer

Oppo

Synopsys

Apple

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3 years ago

Algorithms

3 years ago

Why opt for the Tomasulo Algorithm in scheduling tasks? Any practical experience with it? Please provide an instance of your implementation. How does it tackle pipeline hazards?

Design Verification Engineer

Oppo

Cisco Systems

Bosch

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3 years ago

Chip Design

3 years ago

How would you engineer counters for diverse situations, like a mod-15 counter that bypasses 0, 3, 4, 8, and 5?

Design Verification Engineer

Oppo

Nuro

GlobalFoundries

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3 years ago

Behavioral

3 years ago

Could you highlight some key learnings from the last craft conference you attended?

Design Verification EngineerEmbedded Engineer

Oppo

Micron Technology

Silicon Motion

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3 years ago

Design

3 years ago

Could you explain the selection of assertions for a FIFO design and the critical conditions to evaluate for its smooth functioning?

Design Verification Engineer

Oppo

Philips

ON Semiconductor

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3 years ago

Technical

4 years ago

How do you plan to test the functionality of this ALU black box? What strategies would you use to enhance its performance through superscalar or pipelining techniques?

Design Verification Engineer

Oppo

Micron Technology

Mentor Graphics

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4 years ago

Design

4 years ago

Could you detail the working principle of master/slave agents on a shared bus, with reference to AXI or analogous protocols, especially regarding data integrity and bus contention avoidance?

Design Verification Engineer

Oppo

Aurora

Teradyne

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4 years ago

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Software Engineer

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Product Manager

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Engineering Manager

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Data Scientist

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^*All interview questions are submitted by recent OPPO candidates, labelled and categorized by Prepfully, and then published after verification by current and ex-OPPO employees.