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Embedded System Design
3 years ago
What strategies do you recommend for noise reduction in GPIO transitions?
Embedded Engineer

ON Semiconductor

Lam Research

HP

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3 years ago
Behavioral
3 years ago
What expertise do you hold that makes you a valuable candidate?
Design Verification EngineerEmbedded Engineer

ON Semiconductor

Autodesk Logo

Autodesk

National Instruments Logo

National Instruments

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3 years ago
Technical
4 years ago
Can you provide a case where a virtual interface in SystemVerilog proved beneficial in design verification?
Design Verification Engineer

ON Semiconductor

Novartis Logo

Novartis

GlobalFoundries Logo

GlobalFoundries

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4 years ago
Behavioral
4 years ago
What stands out as your most outstanding achievement?
Design Verification EngineerEmbedded Engineer

ON Semiconductor

Comau Robotics Logo

Comau Robotics

Atlas Copco Logo

Atlas Copco

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4 years ago
Design
4 years ago
Can you illustrate the concept of Floorplanning in VLSI design?
Design Verification Engineer

ON Semiconductor

AMD Logo

AMD

Adobe Logo

Adobe

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4 years ago
CircuitsChip Design
4 years ago
Would you be able to clarify the transfer function of a high pass filter and depict its frequency response curve, explaining the curve's properties?
Embedded Engineer

ON Semiconductor

Cirrus Logic Logo

Cirrus Logic

Panasonic Logo

Panasonic

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4 years ago
Design
4 years ago
In your approach, how do you design interrupt controllers for various processors? How do you sort and prioritize multiple interrupt requests?
Design Verification Engineer

ON Semiconductor

Audi Logo

Audi

Hitachi Logo

Hitachi

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4 years ago
Verilog Coding
4 years ago
What approach would you take to formulate an SVA in System Verilog that certifies a signal's transition from 0 to 1 precedes another's fall from 1 to 0?
Design Verification Engineer

ON Semiconductor

Kawasaki Heavy Industries Logo

Kawasaki Heavy Industries

Philips Healthcare Logo

Philips Healthcare

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4 years ago
Technical
4 years ago
Can you describe the contrast between positive edge and negative edge triggers in Verilog?
Design Verification Engineer

ON Semiconductor

Boston Scientific Logo

Boston Scientific

Teradyne Logo

Teradyne

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4 years ago
Technical
4 years ago
Can you outline the components of the testbench you assembled for a particular project?
Design Verification Engineer

ON Semiconductor

Google Logo

Google

Juul Labs Logo

Juul Labs

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4 years ago

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