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Technical

2 years ago

Can you explain the concept and importance of cache coherence protocols?

Design Verification Engineer

NVIDIA

Cruise

Xiaomi

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2 years ago

Technical

2 years ago

What separates the get_next_item() method from the get() method in UVM's driver class?

Design Verification Engineer

NVIDIA

ABB

Dell

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2 years ago

Circuits

2 years ago

How do you describe a Linear Feedback Shift Register (LFSR) in terms of its operation?

Design Verification Engineer

NVIDIA

Emerson Electric

ABB

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2 years ago

Design

2 years ago

What approach do you take when tasked with designing a priority encoder?

Design Verification Engineer

NVIDIA

Oppo

Synopsys

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2 years ago

Circuits

2 years ago

Can you elucidate the layout of a memory array, the usual tasks of a sense amplifier, and the workings of an equilibration circuit?

Design Verification Engineer

NVIDIA

Cisco

Cisco Systems

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2 years ago

Behavioral

2 years ago

Could you tell us about a decision that didn't turn out as expected? What did you learn through that process?

Design Verification EngineerEmbedded Engineer

NVIDIA

NetApp

Marvell

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2 years ago

Design

2 years ago

What sets apart custom cell design from standard cell design?

Design Verification Engineer

NVIDIA

Tesla

Bosch

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2 years ago

Circuits

2 years ago

How would you go about calculating the depth of a FIFO?

Design Verification Engineer

NVIDIA

KLA

BMW Group

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2 years ago

DesignCircuits

2 years ago

Please provide a Verilog design for a routing circuit with multiple outputs and an enable signal, based on a two-bit input address.

Design Verification Engineer

NVIDIA

KLA

Ducati

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2 years ago

Technical

2 years ago

What is your history with Verilog in design and verification, and can you provide an instance of a project where you applied it?

Design Verification Engineer

NVIDIA

Dell

Philips Healthcare

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2 years ago

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^*All interview questions are submitted by recent NVIDIA Design Verification Engineer candidates, labelled and categorized by Prepfully, and then published after being verified by Design Verification Engineers at NVIDIA.

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