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Technical

4 years ago

Can you elucidate what is meant by an 'event' in Verilog?

Design Verification Engineer

NVIDIA

Taiwan Semiconductor

Northrop Grumman

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4 years ago

Technical

4 years ago

In your experience, how does Verilog handle the aspect of time in simulations?

Design Verification Engineer

NVIDIA

Cadence Design Systems

Ford Motor Company

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4 years ago

Technical

4 years ago

How do Verilog's blocking assignments vary from non-blocking assignments?

Design Verification Engineer

NVIDIA

Medtronic

Xilinx

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4 years ago

Circuits

4 years ago

How can you construct a NAND gate using exclusively 2:1 multiplexers?

Design Verification Engineer

NVIDIA

GlobalFoundries

Bombardier Transportation

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4 years ago

Design

4 years ago

Could you list the pins and their total in a TAP interface of a JTAG boundary scan?

Design Verification Engineer

NVIDIA

Belkin

Hitachi

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4 years ago

Technical

4 years ago

In System Verilog, how are reg, logic, and wire datatypes distinct from each other?

Design Verification Engineer

NVIDIA

Johnson Controls

MediaTek

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4 years ago

Verilog Coding

4 years ago

Could you explain the logic behind the statement "wire #10 a = b & c"?

Design Verification Engineer

NVIDIA

Fujikura

BAE Systems

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4 years ago

Behavioral

4 years ago

Share your experience with a notable failure at work and what it taught you.

Design Verification Engineer

NVIDIA

Safran

IBM

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4 years ago

Algorithms

4 years ago

In what way would you sort a group of 10 integers to ensure they are in ascending order?

Design Verification Engineer

NVIDIA

Seagate Technology

ZTE

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4 years ago

Circuits

4 years ago

How would you differentiate a latch from a flip flop? Please illustrate with an example.

Design Verification Engineer

NVIDIA

Northrop Grumman

Boeing

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4 years ago

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^*All interview questions are submitted by recent NVIDIA Design Verification Engineer candidates, labelled and categorized by Prepfully, and then published after being verified by Design Verification Engineers at NVIDIA.

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