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Design
6 months ago
What's your approach to finding and optimizing the critical path in digital design?
Design Verification Engineer

Mentor Graphics

Bombardier

Silicon Labs

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6 months ago
Circuits
6 months ago
With just the write(addr, data) and read(addr, &data) APIs, how would you engineer a solution to identify a shorted internal signal?
Design Verification Engineer

Mentor Graphics

Legrand Logo

Legrand

Applied Materials Logo

Applied Materials

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6 months ago
Technical
6 months ago
In software development, how would you go about implementing a queue?
Design Verification Engineer

Mentor Graphics

Micron Technology Logo

Micron Technology

AIRBUS Logo

AIRBUS

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6 months ago
Technical
6 months ago
Can you describe the process you follow for a test plan in design verification?
Design Verification Engineer

Mentor Graphics

Yamaha Motor Corporation Logo

Yamaha Motor Corporation

AIRBUS Logo

AIRBUS

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6 months ago
Technical
6 months ago
Can you identify the component in Verilog that modifies simulation time?
Design Verification Engineer

Mentor Graphics

Skyworks Solutions Logo

Skyworks Solutions

Triumph Motorcycles Logo

Triumph Motorcycles

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6 months ago
Algorithms
6 months ago
Can you provide a C++ code example for an LRU cache management policy?
Design Verification Engineer

Mentor Graphics

Fujitsu Logo

Fujitsu

Tesla Logo

Tesla

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6 months ago
Verilog Coding
7 months ago
In what way would you approach implementing a 32-word 2R1W RF with a modifiable bitwidth?
Design Verification Engineer

Mentor Graphics

Sumitomo Electric Logo

Sumitomo Electric

Waymo Logo

Waymo

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7 months ago
Technical Knowledge
7 months ago
How would you describe the use of a semaphore in RTOS?
Embedded Engineer

Mentor Graphics

National Instruments Logo

National Instruments

Goodyear Logo

Goodyear

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7 months ago
Technical
7 months ago
How does the handshake occur between a UVM agent and a UVM sequencer in your experience?
Design Verification Engineer

Mentor Graphics

Microchip Technology Logo

Microchip Technology

Arm Logo

Arm

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7 months ago
Technical
7 months ago
What's your explanation of setup time and hold time, their violation scenarios, and techniques to mitigate such violations?
Design Verification Engineer

Mentor Graphics

Embraer Logo

Embraer

Amazon Logo

Amazon

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7 months ago

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*All interview questions are submitted by recent Mentor Graphics candidates, labelled and categorized by Prepfully, and then published after verification by current and ex-Mentor Graphics employees.

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