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Technical
6 months ago
Can you identify the component in Verilog that modifies simulation time?
Design Verification Engineer

Mentor Graphics

Skyworks Solutions

Triumph Motorcycles

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6 months ago
Algorithms
6 months ago
Can you provide a C++ code example for an LRU cache management policy?
Design Verification Engineer

Mentor Graphics

Fujitsu Logo

Fujitsu

Tesla Logo

Tesla

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6 months ago
Verilog Coding
6 months ago
In what way would you approach implementing a 32-word 2R1W RF with a modifiable bitwidth?
Design Verification Engineer

Mentor Graphics

Sumitomo Electric Logo

Sumitomo Electric

Waymo Logo

Waymo

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6 months ago
Technical
7 months ago
How does the handshake occur between a UVM agent and a UVM sequencer in your experience?
Design Verification Engineer

Mentor Graphics

Microchip Technology Logo

Microchip Technology

Arm Logo

Arm

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7 months ago
Technical
7 months ago
What's your explanation of setup time and hold time, their violation scenarios, and techniques to mitigate such violations?
Design Verification Engineer

Mentor Graphics

Embraer Logo

Embraer

Amazon Logo

Amazon

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7 months ago
Technical
7 months ago
What's your approach to constraint writing in SystemVerilog?
Design Verification Engineer

Mentor Graphics

AT&T Logo

AT&T

Microsoft Logo

Microsoft

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7 months ago
Technical
7 months ago
What is your level of familiarity with UVM and System Verilog?
Design Verification Engineer

Mentor Graphics

Peloton Logo

Peloton

Amazon Logo

Amazon

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7 months ago
Technical
8 months ago
What exactly do scan chains entail?
Design Verification Engineer

Mentor Graphics

ABB Logo

ABB

Keysight Technologies Logo

Keysight Technologies

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8 months ago
Behavioral
9 months ago
Describe a scenario where you exemplified ownership in your duties.
Design Verification EngineerEmbedded Engineer

Mentor Graphics

Waymo Logo

Waymo

Xilinx Logo

Xilinx

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9 months ago
Algorithms
9 months ago
Please describe a method to construct two arrays, each 10 items long, ensuring all elements are distinct.
Design Verification Engineer

Mentor Graphics

Autodesk Logo

Autodesk

TP-Link Logo

TP-Link

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9 months ago

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*All interview questions are submitted by recent Mentor Graphics Design Verification Engineer candidates, labelled and categorized by Prepfully, and then published after being verified by Design Verification Engineers at Mentor Graphics.

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