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Design
a year ago
How would you rate your knowledge of the Ethernet protocol and could you outline its significant features and components?
Design Verification Engineer

Intel

BMW Group

Rockwell Automation

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a year ago
Verilog Coding
a year ago
How would you create assertions to detect numbers that are powers of two?
Design Verification Engineer

Intel

IBM Logo

IBM

Peloton Logo

Peloton

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a year ago
Circuits
a year ago
With a 10MHz square wave as the clock and J=K=0, what output frequency does a JK flip-flop produce?
Design Verification Engineer

Intel

Western Digital Logo

Western Digital

Alstom Logo

Alstom

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a year ago
Technical
2 years ago
What are the functional differences between the 'new' and 'create' methods in UVM?
Design Verification Engineer

Intel

Fujitsu Logo

Fujitsu

GlobalFoundries Logo

GlobalFoundries

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2 years ago
Circuits
2 years ago
Can you explain how to measure the depth of a FIFO?
Design Verification Engineer

Intel

KLA Logo

KLA

BMW Group

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2 years ago
Verilog Coding
2 years ago
In System Verilog, what's your strategy for ensuring through an SVA that a FIFO is entirely empty before reading begins?
Design Verification Engineer

Intel

Huawei Logo

Huawei

Autodesk Logo

Autodesk

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2 years ago
Behavioral
2 years ago
Please describe a time when you had difficulty meeting a deadline. How did you address this challenge?
Design Verification Engineer

Intel

Aurora Logo

Aurora

Oracle Logo

Oracle

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2 years ago
Technical
2 years ago
Can you recall a situation where the use of a virtual interface in SystemVerilog was effective for design verification?
Design Verification Engineer

Intel

Novartis Logo

Novartis

GlobalFoundries Logo

GlobalFoundries

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2 years ago
Technical
2 years ago
What separates Immediate Assertions from Concurrent Assertions in the context of SystemVerilog?
Design Verification Engineer

Intel

Skyworks Solutions Logo

Skyworks Solutions

Eaton Logo

Eaton

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2 years ago
Behavioral
2 years ago
What stands out as your most outstanding achievement?
Design Verification EngineerEmbedded Engineer

Intel

Comau Robotics Logo

Comau Robotics

Atlas Copco Logo

Atlas Copco

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2 years ago

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*All interview questions are submitted by recent Intel Design Verification Engineer candidates, labelled and categorized by Prepfully, and then published after being verified by Design Verification Engineers at Intel.

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