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Technical

2 years ago

Can you explain the workings of a single-channel DMA controller? Also, how does it manage multiple parallel channels and peripherals?

Design Verification Engineer

Intel

Sony

Marvell

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2 years ago

Design

2 years ago

Can you discuss your approach to designing interrupt controllers for various processors? How do you manage and prioritize multiple interrupt requests?

Design Verification Engineer

Intel

Audi

Hitachi

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2 years ago

Circuits

2 years ago

Given only write(addr, data) and read(addr, &data) APIs, how do you plan to uncover a shorted internal signal in a device?

Design Verification Engineer

Intel

Legrand

Applied Materials

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2 years ago

Algorithms

2 years ago

In what way can you produce two non-overlapping arrays, each with a length of 10?

Design Verification Engineer

Intel

Autodesk

TP-Link

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2 years ago

CircuitsDesign

2 years ago

In your process of designing a circuit with adders and gates, what factors do you take into account?

Design Verification Engineer

Intel

Amgen

ASUS

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2 years ago

Verilog Coding

2 years ago

In System Verilog, how do you ensure through an SVA that one signal goes from 0 to 1 before another reverses from 1 to 0?

Design Verification Engineer

Intel

Kawasaki Heavy Industries

Philips Healthcare

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2 years ago

Circuits

2 years ago

Can you construct the truth table representing a NAND gate's logic?

Design Verification Engineer

Intel

Xilinx

Sumitomo Electric

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2 years ago

Technical

2 years ago

What benefits do assertions bring to our processes?

Design Verification Engineer

Intel

Fujikura

Agilent Technologies

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2 years ago

Behavioral

2 years ago

What methods have you found effective in gaining your team's trust?

Design Verification EngineerEmbedded Engineer

Intel

GlobalFoundries

Fujitsu

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2 years ago

Behavioral

2 years ago

What metrics would you use to define success?

Design Verification EngineerEmbedded Engineer

Intel

Amazon

Synopsys

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2 years ago

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