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Verilog Coding
3 years ago
What methodology would you apply to construct a 32-word 2R1W register file with programmable bitwidth?
Design Verification Engineer

GE Aviation

Sumitomo Electric

Waymo

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3 years ago
Design
3 years ago
What are the essential elements you consider when designing a priority encoder?
Design Verification Engineer

GE Aviation

Oppo

Synopsys

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3 years ago
Design
3 years ago
What's your methodology for verifying a black box and how do you develop a test plan?
Design Verification Engineer

GE Aviation

Johnson Controls Logo

Johnson Controls

General Electric Logo

General Electric

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3 years ago
Verilog Coding
3 years ago
Can you develop HDL code for a 3-state FSM (IDLE, READ, WRITE), with transitions based on the "op" input signal and a 4-clock-cycle return to IDLE?
Design Verification Engineer

GE Aviation

NXP Semiconductors Logo

NXP Semiconductors

NVIDIA Logo

NVIDIA

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3 years ago
Technical
3 years ago
What distinguishes a FinFET from a typical MOSFET?
Design Verification Engineer

GE Aviation

Zoox Logo

Zoox

Synopsys

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3 years ago
Technical
3 years ago
How do Karnaugh maps facilitate the simplification of Boolean expressions in your experience?
Design Verification Engineer

GE Aviation

Agilent Technologies Logo

Agilent Technologies

Lam Research Logo

Lam Research

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3 years ago
Design
3 years ago
Please describe how delay and slew rate vary in VLSI design.
Design Verification Engineer

GE Aviation

Sony Logo

Sony

Northrop Grumman Logo

Northrop Grumman

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3 years ago
Technical
3 years ago
In your own words, how would you explain clock domain crossing and its challenges?
Design Verification Engineer

GE Aviation

Northrop Grumman Logo

Northrop Grumman

Western Digital Logo

Western Digital

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3 years ago
Circuits
3 years ago
Why are D-flipflops and similar devices usually built with NAND gates instead of NOR gates?
Design Verification Engineer

GE Aviation

Rockwell Collins Logo

Rockwell Collins

Northrop Grumman Logo

Northrop Grumman

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3 years ago
Technical
3 years ago
Can you discuss the UVM RAL model and explain why it is a crucial component?
Design Verification Engineer

GE Aviation

Sumitomo Electric

KLA Logo

KLA

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3 years ago

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