Prepfully logo
  • Browse Coaches
  • Login
BetaTry Out Our New AI Mock Interviewer – Your Smartest Way to Ace Any Interview!Try Our AI Mock Interviewer
Try Now
NewRegister as a coach and get a $100 bonus on your first completed session if you're on the Prepfully Request for Coaches list.Coach $100 Bonus
Read More
LimitedEaster Deal: Heavy discounts on all Prepfully sessions.Easter Deal: Discounts
Book Now

Your AI Wingman for your next interview

The most comprehensive bank Interview Answer Review tooling available online.

Cutting-edge AI technology meets personalized feedback. Improve your interview answers with insightful guidance provided by a model trained against more than a million human-labelled interview answers.
  • Company rubrics
  • Role-level optimisations
  • Trained on 1mil+ answers
Behavioral
3 years ago
Could you tell us about a decision that didn't turn out as expected? What did you learn through that process?
Design Verification EngineerEmbedded Engineer

GE Aviation

NetApp

Marvell

Get answer reviewed by AI
3 years ago
Verilog Coding
3 years ago
Can you demonstrate how to construct a System Verilog Assertion that validates a signal's shift from 0 to 1 occurs before a different signal changes from 1 to 0?
Design Verification Engineer

GE Aviation

Kawasaki Heavy Industries

Philips Healthcare

Get answer reviewed by AI
3 years ago
Technical
3 years ago
Can you detail the principles and application of Transaction-level modeling in UVM?
Design Verification Engineer

GE Aviation

Juniper Networks Logo

Juniper Networks

Volkswagen Logo

Volkswagen

Get answer reviewed by AI
3 years ago
Verilog Coding
3 years ago
What's your methodology for developing a behavioral model in Verilog?
Design Verification Engineer

GE Aviation

Philips Logo

Philips

Peloton Logo

Peloton

Get answer reviewed by AI
3 years ago
Design
3 years ago
What is your approach to developing a 3 bit shift register using verilog RTL?
Design Verification Engineer

GE Aviation

NETGEAR Logo

NETGEAR

Infineon Logo

Infineon

Get answer reviewed by AI
3 years ago
Verilog Coding
3 years ago
What are the different approaches to implementing delays in Verilog, and can you provide examples?
Design Verification Engineer

GE Aviation

STMicroelectronics Logo

STMicroelectronics

Hewlett Packard Logo

Hewlett Packard

Get answer reviewed by AI
3 years ago
Verilog Coding
3 years ago
How do you construct an SVA in System Verilog to avert memory transactions during a power-on-reset phase?
Design Verification Engineer

GE Aviation

Xilinx Logo

Xilinx

Ericsson Logo

Ericsson

Get answer reviewed by AI
3 years ago
Design
3 years ago
What separates a monitor from a scoreboard in the UVM environment?
Design Verification Engineer

GE Aviation

Renesas Electronics Logo

Renesas Electronics

ASUS Logo

ASUS

Get answer reviewed by AI
3 years ago
Verilog Coding
3 years ago
In your interpretation, what is the significance of "wire #10 a = b & c"?
Design Verification Engineer

GE Aviation

Fujikura Logo

Fujikura

BAE Systems Logo

BAE Systems

Get answer reviewed by AI
3 years ago
Chip Design
3 years ago
Can you describe the process of designing a D flip-flop with a multiplexer?
Design Verification Engineer

GE Aviation

Novartis Logo

Novartis

Blue Origin Logo

Blue Origin

Get answer reviewed by AI
3 years ago

Question of the week

We'll send you a weekly question to practice for:

Showing 111 to 120 of 176 results

Previous1011121314Next

*All interview questions are submitted by recent GE Aviation candidates, labelled and categorized by Prepfully, and then published after verification by current and ex-GE Aviation employees.

  • Company
  • FAQs
  • Contact Us
  • Become An Expert
  • Services
  • Practice Interviews
  • Interview Guides
  • Interview Questions
  • Watch Recorded Interviews
  • Gift sessions
  • AI Interview
  • Social
  • Twitter
  • Facebook
  • LinkedIn
  • YouTube
  • Legal
  • Terms & Conditions
  • Privacy Policy
  • Illustrations by Storyset

© 2025 Prepfully. All rights reserved.

Prepfully logo

Please log in to view more questions.

Not a member yet? Sign up for free.