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Technical
2 years ago
In your experience, how do code coverage and functional coverage vary?
Design Verification Engineer
GE Aviation Logo

GE Aviation

Amazon Logo

Amazon

Siemens Logo

Siemens

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2 years ago
Behavioral
2 years ago
Walk me through a situation where you made an immediate decision.
Design Verification EngineerEmbedded Engineer
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GE Aviation

Philips Logo

Philips

LG Electronics Logo

LG Electronics

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2 years ago
Algorithms
2 years ago
How would you go about arranging 10 numbers in an order that goes from smallest to largest?
Design Verification Engineer
GE Aviation Logo

GE Aviation

Seagate Technology Logo

Seagate Technology

ZTE Logo

ZTE

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2 years ago
Technical
2 years ago
Can you explain the steps for defining constraints in SystemVerilog?
Design Verification Engineer
GE Aviation Logo

GE Aviation

AT&T Logo

AT&T

Microsoft Logo

Microsoft

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2 years ago
Technical
2 years ago
Could you detail the various timing violations that can manifest in RTL designs?
Design Verification Engineer
GE Aviation Logo

GE Aviation

Qualcomm Logo

Qualcomm

Acer Logo

Acer

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2 years ago
Design
2 years ago
Why is parasitic resistance critical in VLSI design?
Design Verification Engineer
GE Aviation Logo

GE Aviation

NXP Semiconductors Logo

NXP Semiconductors

Prysmian Group Logo

Prysmian Group

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2 years ago
Design
2 years ago
What are the adders you've encountered in VLSI design? How do you optimize these for diverse application scenarios?
Design Verification Engineer
GE Aviation Logo

GE Aviation

National Instruments Logo

National Instruments

Emerson Electric Logo

Emerson Electric

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2 years ago
Technical
2 years ago
How do you identify and cover a coverage point in your verification environment? Give an example.
Design Verification Engineer
GE Aviation Logo

GE Aviation

Prysmian Group Logo

Prysmian Group

FLIR Systems Logo

FLIR Systems

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2 years ago
Technical
2 years ago
What is your expertise in implementing and verifying arbitration logic, and what kinds of challenges have you faced?
Design Verification Engineer
GE Aviation Logo

GE Aviation

Panasonic Logo

Panasonic

Leidos Logo

Leidos

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2 years ago
Technical
2 years ago
What's your understanding of a cache and its operational dynamics?
Design Verification Engineer
GE Aviation Logo

GE Aviation

Garmin Logo

Garmin

Keysight Technologies Logo

Keysight Technologies

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2 years ago

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*All interview questions are submitted by recent GE Aviation Design Verification Engineer candidates, labelled and categorized by Prepfully, and then published after being verified by Design Verification Engineers at GE Aviation.

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