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Verilog Coding
a year ago
How is a behavioral model constructed in Verilog? Could you detail the process?
Design Verification Engineer
AT&T Logo

AT&T

Cirrus Logic Logo

Cirrus Logic

Nokia Logo

Nokia

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a year ago
Design
a year ago
Can you delineate the distinctions between custom and standard cell design?
Design Verification Engineer
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AT&T

Micron Technology Logo

Micron Technology

Varian Medical Systems Logo

Varian Medical Systems

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a year ago
Technical
a year ago
How does one customize the duration of a simulation in Verilog?
Design Verification Engineer
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AT&T

CRRC Logo

CRRC

Garmin Logo

Garmin

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a year ago
Circuits
a year ago
Could you provide a graphical representation of the IDD of an inverter as it goes from OFF to ON?
Design Verification Engineer
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AT&T

Sony Logo

Sony

Beckman Coulter Logo

Beckman Coulter

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a year ago
Algorithms
a year ago
How would you code the Fibonacci series in C++?
Design Verification Engineer
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AT&T

Embraer Logo

Embraer

Silicon Labs Logo

Silicon Labs

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a year ago
Circuits
a year ago
What do the propagation delay terms C2Q, S2Q, and R2Q signify in flip-flops?
Design Verification Engineer
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AT&T

GlobalFoundries Logo

GlobalFoundries

Bombardier Transportation Logo

Bombardier Transportation

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a year ago
Technical
a year ago
In your own words, how would you describe a cache and its mechanism of action?
Design Verification Engineer
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AT&T

Polaris Industries Logo

Polaris Industries

Zoox Logo

Zoox

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a year ago
Circuits
a year ago
How can you utilize write(addr, data) and read(addr, &data) APIs to detect a shorted internal signal, assuming black box constraints?
Design Verification Engineer
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AT&T

Sumitomo Electric Logo

Sumitomo Electric

Sharp Logo

Sharp

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a year ago
Technical
a year ago
What makes a positive edge trigger different from a negative edge trigger in Verilog?
Design Verification Engineer
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AT&T

National Instruments Logo

National Instruments

Northrop Grumman Logo

Northrop Grumman

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a year ago
Technical
a year ago
What distinguishes SystemVerilog assertions from UVM assertions?
Design Verification Engineer
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AT&T

Garmin Logo

Garmin

Becton Dickinson Logo

Becton Dickinson

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a year ago

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*All interview questions are submitted by recent AT&T Design Verification Engineer candidates, labelled and categorized by Prepfully, and then published after being verified by Design Verification Engineers at AT&T.

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