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Technical
5 months ago
How does UVM approach reusability and scalability in the context of verification?
Design Verification Engineer
AT&T Logo

AT&T

Nuro Logo

Nuro

FLIR Systems Logo

FLIR Systems

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5 months ago
Circuits
6 months ago
Outline the principle of a multiplexer, using a circuit diagram for explanation.
Design Verification Engineer
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AT&T

Leidos Logo

Leidos

Taiwan Semiconductor Logo

Taiwan Semiconductor

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6 months ago
Technical
6 months ago
What do you understand by the term 'metastability'?
Design Verification Engineer
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AT&T

Arista Networks Logo

Arista Networks

Alstom Logo

Alstom

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6 months ago
Technical
7 months ago
What's the rationale behind preferring the create method over the new constructor in UVM?
Design Verification Engineer
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AT&T

Peloton Logo

Peloton

Yamaha Motor Corporation Logo

Yamaha Motor Corporation

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7 months ago
Technical
7 months ago
In your experience, how do reg, logic, and wire vary in System Verilog?
Design Verification Engineer
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AT&T

Hewlett Packard Logo

Hewlett Packard

Nokia Logo

Nokia

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7 months ago
Behavioral
7 months ago
Could you tell us about a decision that didn't turn out as expected? What did you learn through that process?
Design Verification EngineerEmbedded Engineer
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AT&T

MediaTek Logo

MediaTek

Schneider Electric Logo

Schneider Electric

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7 months ago
Circuits
7 months ago
How do the voltages of two parallel capacitors, each with a distinct charge, react when the connecting transistor is engaged?
Design Verification Engineer
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AT&T

Juniper Networks Logo

Juniper Networks

ABB Logo

ABB

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7 months ago
Technical
7 months ago
Could you explain the contrast between module-based and class-based Testbenches?
Design Verification Engineer
AT&T Logo

AT&T

TP-Link Logo

TP-Link

SpaceX Logo

SpaceX

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7 months ago
Behavioral
8 months ago
Could you discuss some significant learnings from a recent craft conference you attended?
Design Verification EngineerEmbedded Engineer
AT&T Logo

AT&T

ON Semiconductor Logo

ON Semiconductor

Logitech Logo

Logitech

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8 months ago
Verilog Coding
8 months ago
What Verilog constructs are frequently used in the creation of verification environments?
Design Verification Engineer
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AT&T

Juul Labs Logo

Juul Labs

Toshiba Logo

Toshiba

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8 months ago

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*All interview questions are submitted by recent AT&T Design Verification Engineer candidates, labelled and categorized by Prepfully, and then published after being verified by Design Verification Engineers at AT&T.

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