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Design

4 years ago

Can you elaborate on the importance of parasitic resistance in VLSI design?

Design Verification Engineer

AT&T

NXP Semiconductors

Prysmian Group

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4 years ago

Technical

4 years ago

How do you plan to tackle a bug that's been reported by the verification team?

Design Verification Engineer

AT&T

Cirrus Logic

Panasonic

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4 years ago

Verilog Coding

4 years ago

Can you describe the different methods for implementing delays in Verilog, perhaps with some examples?

Design Verification Engineer

AT&T

STMicroelectronics

Hewlett Packard

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4 years ago

Chip Design

4 years ago

Plan out counters for assorted scenarios, like a mod-15 counter excluding 0, 3, 4, 8, and 5 from its count.

Design Verification Engineer

AT&T

Nuro

GlobalFoundries

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4 years ago

Verilog Coding

4 years ago

How do you envision coding a HDL FSM with IDLE, READ, WRITE states, changing states on "op" input and returning to IDLE after 4 clock cycles?

Design Verification Engineer

AT&T

NXP Semiconductors

NVIDIA

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4 years ago

Design

4 years ago

What is your approach to developing a 3 bit shift register using verilog RTL?

Design Verification Engineer

AT&T

NETGEAR

Infineon

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4 years ago

Behavioral

4 years ago

What community holds your interest and passion? Given the opportunity, how would you contribute to it?

Design Verification EngineerEmbedded Engineer

AT&T

Adobe

Northrop Grumman

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4 years ago

Design

4 years ago

How well do you know the Ethernet protocol and can you describe some of its critical features and components?

Design Verification Engineer

AT&T

BMW Group

Rockwell Automation

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4 years ago

Circuits

4 years ago

What frequency can be expected at the output of a JK flip-flop with J=K=0 and a clock frequency of 10MHz?

Design Verification Engineer

AT&T

Western Digital

Alstom

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4 years ago

Design

4 years ago

Can you outline the steps in the RTL design flow process?

Design Verification Engineer

AT&T

Microsoft

Hitachi

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4 years ago

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^*All interview questions are submitted by recent AT&T Design Verification Engineer candidates, labelled and categorized by Prepfully, and then published after being verified by Design Verification Engineers at AT&T.

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