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Circuits

3 years ago

How does the output of a pulse generator, which includes a NAND gate and input delay from inverters, reflect the input timing diagram?

Design Verification Engineer

AT&T

Lattice Semiconductor

Thermo Fisher Scientific

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3 years ago

Verilog Coding

3 years ago

Construct assertions to filter numbers that are exact powers of 2.

Design Verification Engineer

AT&T

IBM

Peloton

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3 years ago

Design

3 years ago

Could you detail the working principle of master/slave agents on a shared bus, with reference to AXI or analogous protocols, especially regarding data integrity and bus contention avoidance?

Design Verification Engineer

AT&T

Aurora

Teradyne

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3 years ago

Verilog Coding

3 years ago

How would you script Verilog code for a detector that identifies positive and negative edges?

Design Verification Engineer

AT&T

Medtronic

D-Link

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3 years ago

Verilog Coding

3 years ago

How would you frame an SVA in System Verilog to validate the timing order of a signal going from 0 to 1, preceding another's switch from 1 to 0?

Design Verification Engineer

AT&T

Kawasaki Heavy Industries

Philips Healthcare

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3 years ago

Circuits

3 years ago

What's your approach to building a NAND gate with only 2:1 MUXes?

Design Verification Engineer

AT&T

GlobalFoundries

Bombardier Transportation

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3 years ago

Verilog Coding

3 years ago

What methodology would you use to create a binary to thermometer decoder using Verilog?

Design Verification Engineer

AT&T

Bosch

Fujikura

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3 years ago

Design

3 years ago

In a JTAG boundary scan, how many pins does the TAP interface have, and what are they?

Design Verification Engineer

AT&T

Belkin

Hitachi

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3 years ago

Technical

3 years ago

Can you describe your process for IP verification? If a new IP is incorporated into your design, how do you go about verifying it?

Design Verification Engineer

AT&T

Aurora

Sharp

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3 years ago

Technical

3 years ago

Can you differentiate between the # directive and the $timeformat directive in Verilog?

Design Verification Engineer

AT&T

Aurora

General Electric

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3 years ago

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^*All interview questions are submitted by recent AT&T Design Verification Engineer candidates, labelled and categorized by Prepfully, and then published after being verified by Design Verification Engineers at AT&T.

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