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Behavioral
7 months ago
Can you discuss how you balance your tasks in your current role?
Design Verification EngineerEmbedded Engineer
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AMD

Honeywell Logo

Honeywell

Silicon Motion Logo

Silicon Motion

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7 months ago
Technical
7 months ago
What kinds of timing violations are typically seen in RTL designs?
Design Verification Engineer
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AMD

GlobalFoundries Logo

GlobalFoundries

Yokogawa Electric Logo

Yokogawa Electric

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7 months ago
Technical
8 months ago
How does a register table play a role in the design of embedded systems?
Design Verification Engineer
AMD Logo

AMD

Skyworks Solutions Logo

Skyworks Solutions

Bombardier Logo

Bombardier

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8 months ago
Technical
8 months ago
Can you explain how you would rectify a setup and hold time violation?
Design Verification Engineer
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AMD

STMicroelectronics Logo

STMicroelectronics

Autodesk Logo

Autodesk

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8 months ago
Technical
9 months ago
Can you describe the various applications where counters are used?
Design Verification Engineer
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AMD

National Instruments Logo

National Instruments

Hewlett Packard Logo

Hewlett Packard

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9 months ago
Technical
9 months ago
Can you describe your background in using Verilog for design and verification, including a project example?
Design Verification Engineer
AMD Logo

AMD

Boeing Logo

Boeing

Beckman Coulter Logo

Beckman Coulter

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9 months ago
Technical
9 months ago
In your experience, how does Verilog handle the aspect of time in simulations?
Design Verification Engineer
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AMD

Rockwell Collins Logo

Rockwell Collins

Nuro Logo

Nuro

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9 months ago
Behavioral
9 months ago
Could you detail a specific conflict situation and your approach to resolving it?
Design Verification EngineerEmbedded Engineer
AMD Logo

AMD

Mentor Graphics Logo

Mentor Graphics

Varian Medical Systems Logo

Varian Medical Systems

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9 months ago
Technical
9 months ago
Could you detail the unique aspects of SystemVerilog assertions compared to UVM assertions?
Design Verification Engineer
AMD Logo

AMD

Garmin Logo

Garmin

Becton Dickinson Logo

Becton Dickinson

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9 months ago
Verilog Coding
10 months ago
In System Verilog, how do you construct an SVA to block transaction initiation while the reset signal is active?
Design Verification Engineer
AMD Logo

AMD

Xilinx Logo

Xilinx

Schneider Electric Logo

Schneider Electric

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10 months ago

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*All interview questions are submitted by recent AMD Design Verification Engineer candidates, labelled and categorized by Prepfully, and then published after being verified by Design Verification Engineers at AMD.

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