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Computer Architecture
5 months ago
How do pipelining and parallel processing differ in computer architecture?
Design Verification Engineer
AMD Logo

AMD

Akamai Logo

Akamai

Abbott Laboratories Logo

Abbott Laboratories

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5 months ago
Behavioral
5 months ago
Can you give a swift overview of your career so far?
Design Verification EngineerEmbedded Engineer
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AMD

Cirrus Logic Logo

Cirrus Logic

Sanmina Logo

Sanmina

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5 months ago
Behavioral
5 months ago
What tactics do you employ to earn the trust of your team?
Design Verification EngineerEmbedded Engineer
AMD Logo

AMD

ON Semiconductor Logo

ON Semiconductor

Synopsys Logo

Synopsys

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5 months ago
Design
5 months ago
Describe bit manipulation and its practical application in one of your previous projects.
Design Verification Engineer
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AMD

IBM Logo

IBM

Legrand Logo

Legrand

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5 months ago
Technical
5 months ago
In Verilog, what exactly is an event?
Design Verification Engineer
AMD Logo

AMD

Renesas Electronics Logo

Renesas Electronics

FLIR Systems Logo

FLIR Systems

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5 months ago
Design
5 months ago
Describe the roles of master and slave agents in a shared bus environment using protocols like AXI, and your approach to ensuring data integrity and preventing bus contention.
Design Verification Engineer
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AMD

Hitachi Logo

Hitachi

Dell Technologies Logo

Dell Technologies

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5 months ago
Algorithms
6 months ago
Why choose the Tomasulo Algorithm over other scheduling techniques? Have you applied it in your work? Could you give an implementation example? How does it manage pipeline hazards?
Design Verification Engineer
AMD Logo

AMD

HP Logo

HP

Meta Logo

Meta

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6 months ago
Verilog Coding
6 months ago
Could you devise an SVA in System Verilog to confirm an input signal's compliance with setup and hold timings?
Design Verification Engineer
AMD Logo

AMD

Juniper Networks Logo

Juniper Networks

Raymarine Logo

Raymarine

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6 months ago
Behavioral
7 months ago
Think of an instance where you had to get someone on board with your idea. How did you go about it?
Design Verification EngineerEmbedded Engineer
AMD Logo

AMD

RS Components Logo

RS Components

STMicroelectronics Logo

STMicroelectronics

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7 months ago
Technical
7 months ago
Could you explain the difference between positive edge triggering and negative edge triggering in Verilog?
Design Verification Engineer
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AMD

National Instruments Logo

National Instruments

Northrop Grumman Logo

Northrop Grumman

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7 months ago

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*All interview questions are submitted by recent AMD Design Verification Engineer candidates, labelled and categorized by Prepfully, and then published after being verified by Design Verification Engineers at AMD.

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