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Technical
7 months ago
Can you explain the rationale behind the use of virtual interfaces in SV?
Design Verification Engineer
Amazon Web Services Logo

Amazon Web Services

Bombardier Transportation Logo

Bombardier Transportation

Prysmian Group Logo

Prysmian Group

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7 months ago
Circuits
7 months ago
Given only write(addr, data) and read(addr, &data) APIs, how do you plan to uncover a shorted internal signal in a device?
Design Verification Engineer
Amazon Web Services Logo

Amazon Web Services

Sumitomo Electric Logo

Sumitomo Electric

Sharp Logo

Sharp

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7 months ago
Design
8 months ago
How would you define parasitic resistance and its importance in VLSI design?
Design Verification Engineer
Amazon Web Services Logo

Amazon Web Services

Huawei Logo

Huawei

Marvell Logo

Marvell

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8 months ago
Verilog Coding
8 months ago
Create SV code specifically for acquiring unique random numbers.
Design Verification Engineer
Amazon Web Services Logo

Amazon Web Services

AIRBUS Logo

AIRBUS

Synopsys Logo

Synopsys

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8 months ago
Circuits
9 months ago
What makes NAND gates the preferred choice for D-flipflops rather than NOR gates?
Design Verification Engineer
Amazon Web Services Logo

Amazon Web Services

Becton Dickinson Logo

Becton Dickinson

Alstom Logo

Alstom

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9 months ago
DesignCircuits
9 months ago
What’s your strategy for creating a circuit that assesses divisibility by three?
Design Verification Engineer
Amazon Web Services Logo

Amazon Web Services

NXP Semiconductors Logo

NXP Semiconductors

Yokogawa Electric Logo

Yokogawa Electric

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9 months ago
Algorithms
9 months ago
Could you demonstrate how you would implement an LRU cache policy in C++?
Design Verification Engineer
Amazon Web Services Logo

Amazon Web Services

NEC Logo

NEC

Yokogawa Electric Logo

Yokogawa Electric

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9 months ago
Technical
10 months ago
Can you identify the component in Verilog that modifies simulation time?
Design Verification Engineer
Amazon Web Services Logo

Amazon Web Services

CRRC Logo

CRRC

Garmin Logo

Garmin

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10 months ago
Design
10 months ago
In your own words, how would you describe the synthesis flow and its function within VLSI design?
Design Verification Engineer
Amazon Web Services Logo

Amazon Web Services

Mercedes-Benz Logo

Mercedes-Benz

GlobalFoundries Logo

GlobalFoundries

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10 months ago
Algorithms
a year ago
What makes Perl advantageous when compared to alternative scripting languages?
Design Verification Engineer
Amazon Web Services Logo

Amazon Web Services

HP Logo

HP

Rohde & Schwarz Logo

Rohde & Schwarz

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a year ago

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*All interview questions are submitted by recent Amazon Web Services Design Verification Engineer candidates, labelled and categorized by Prepfully, and then published after being verified by Design Verification Engineers at Amazon Web Services.

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