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Design
2 years ago
What is the role of master and slave agents on a shared bus in systems like AXI, and how would you approach maintaining data integrity and avoiding bus contention?
Design Verification Engineer

AIRBUS

Aurora

Teradyne

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2 years ago
Technical
2 years ago
Can you clarify the contrast between the # and $timeformat directives in Verilog?
Design Verification Engineer

AIRBUS

Aurora

General Electric

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2 years ago
Circuits
2 years ago
Can you clarify why NAND gates are favored in D-flipflops over NOR gates?
Design Verification Engineer

AIRBUS

Rockwell Collins Logo

Rockwell Collins

Northrop Grumman Logo

Northrop Grumman

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2 years ago
Technical
2 years ago
What is your expertise in implementing and verifying arbitration logic, and what kinds of challenges have you faced?
Design Verification Engineer

AIRBUS

Panasonic Logo

Panasonic

Leidos Logo

Leidos

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2 years ago
Circuits
2 years ago
What changes occur in the output of a pulse generator circuit, which includes a NAND gate and delayed inputs, when you consider the input timing diagram?
Design Verification Engineer

AIRBUS

Lattice Semiconductor Logo

Lattice Semiconductor

Thermo Fisher Scientific Logo

Thermo Fisher Scientific

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2 years ago
Technical
2 years ago
Can you explain the rationale behind the use of virtual interfaces in SV?
Design Verification Engineer

AIRBUS

General Electric

IBM Logo

IBM

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2 years ago
Design
2 years ago
What is your approach to developing a 3 bit shift register using verilog RTL?
Design Verification Engineer

AIRBUS

NETGEAR Logo

NETGEAR

Infineon Logo

Infineon

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2 years ago
Circuits
2 years ago
In what way can you use 2:1 multiplexers to form a NAND gate?
Design Verification Engineer

AIRBUS

GlobalFoundries Logo

GlobalFoundries

Bombardier Transportation Logo

Bombardier Transportation

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2 years ago
Technical
2 years ago
How do you propose to resolve violations of setup and hold times?
Design Verification Engineer

AIRBUS

Yamaha Motor Corporation Logo

Yamaha Motor Corporation

Pratt & Whitney Logo

Pratt & Whitney

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2 years ago
Behavioral
2 years ago
How have you dealt with a difficult situation in a past role where you had extensive responsibilities?
Design Verification EngineerEmbedded Engineer

AIRBUS

KTM AG Logo

KTM AG

Canon Logo

Canon

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2 years ago

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Software Engineer

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Product Manager

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Product Strategy
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AIRBUS

Engineering Manager

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System Design
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AIRBUS

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DS Analytical Execution

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