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Behavioral
8 months ago
Think of a time when a choice you made wasn't effective. How did you grow from this experience?
Embedded EngineerDesign Verification Engineer

ZTE

NetApp

Marvell

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8 months ago
Embedded Coding
8 months ago
Which bitwise operators do you know and understand?
Embedded Engineer
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ZTE

General Electric Logo

General Electric

HARMAN International Logo

HARMAN International

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8 months ago
Technical
8 months ago
What has been your exposure to Verilog in terms of design and verification, and can you mention a specific project involving Verilog?
Design Verification Engineer
ZTE Logo

ZTE

Dell Logo

Dell

Philips Healthcare Logo

Philips Healthcare

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8 months ago
Behavioral
8 months ago
What makes you stand out as the ideal candidate for the Design Verification Engineer position?
Design Verification Engineer
ZTE Logo

ZTE

D-Link Logo

D-Link

Analog Devices Logo

Analog Devices

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8 months ago
Behavioral
8 months ago
Tell us about a moment you chose a risky path over a safe one.
Design Verification EngineerEmbedded Engineer
ZTE Logo

ZTE

Raymarine Logo

Raymarine

Meta Logo

Meta

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8 months ago
Technical
8 months ago
Please provide a detailed explanation of what a Testbench is.
Design Verification Engineer
ZTE Logo

ZTE

Broadcom Logo

Broadcom

Philips Healthcare Logo

Philips Healthcare

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8 months ago
Algorithms
8 months ago
Can you provide a C++ code example for an LRU cache management policy?
Design Verification Engineer
ZTE Logo

ZTE

Fujitsu Logo

Fujitsu

Tesla Logo

Tesla

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8 months ago
Technical
9 months ago
In what case was a virtual interface in SystemVerilog instrumental in achieving successful design verification?
Design Verification Engineer
ZTE Logo

ZTE

Novartis Logo

Novartis

GlobalFoundries Logo

GlobalFoundries

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9 months ago
Behavioral
9 months ago
What methods do you employ to deal with your current work responsibilities?
Design Verification EngineerEmbedded Engineer
ZTE Logo

ZTE

Pratt & Whitney Logo

Pratt & Whitney

OMRON Logo

OMRON

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9 months ago
Verilog Coding
9 months ago
How do you construct an SVA in System Verilog to check a signal's transition from low to high before another goes from high to low?
Design Verification Engineer
ZTE Logo

ZTE

Kawasaki Heavy Industries Logo

Kawasaki Heavy Industries

Philips Healthcare Logo

Philips Healthcare

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9 months ago

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