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Technical
5 months ago
Why do we opt for mailboxes rather than queues in communicating between TB components?
Design Verification Engineer
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Verizon

Abbott Laboratories Logo

Abbott Laboratories

Mentor Graphics Logo

Mentor Graphics

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5 months ago
Design
5 months ago
I'd like to understand the function of transceivers and arbiters. How do you maintain data accuracy and lower power usage?
Design Verification Engineer
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Verizon

Siemens Logo

Siemens

Analog Devices Logo

Analog Devices

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5 months ago
Design
5 months ago
Could you illustrate the process of constructing a 3 bit shift register in verilog RTL?
Design Verification Engineer
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Verizon

CRRC Logo

CRRC

Dell Logo

Dell

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5 months ago
Technical
6 months ago
Can you identify the applications for a lock-up latch?
Design Verification Engineer
Verizon Logo

Verizon

Mitsubishi Electric Logo

Mitsubishi Electric

General Motors Logo

General Motors

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6 months ago
Verilog Coding
6 months ago
How would you engineer a 32-word 2R1W register file with an adjustable bitwidth?
Design Verification Engineer
Verizon Logo

Verizon

Emerson Electric Logo

Emerson Electric

Juniper Networks Logo

Juniper Networks

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6 months ago
Technical
6 months ago
What separates the get_next_item() method from the get() method in UVM's driver class?
Design Verification Engineer
Verizon Logo

Verizon

Ericsson Logo

Ericsson

Waymo Logo

Waymo

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6 months ago
Technical
7 months ago
Can you identify the radix in the equation 121(r) = 144(8)?
Design Verification Engineer
Verizon Logo

Verizon

Dell Logo

Dell

NetApp Logo

NetApp

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7 months ago
Algorithms
7 months ago
Can you discuss the advantages of the Tomasulo Algorithm compared to others? Have you used it in practice? Please share an implementation scenario. How does it address pipeline hazards?
Design Verification Engineer
Verizon Logo

Verizon

HP Logo

HP

Meta Logo

Meta

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7 months ago
Behavioral
7 months ago
Narrate an instance that demanded a quick decision from you.
Design Verification EngineerEmbedded Engineer
Verizon Logo

Verizon

Cadence Design Systems Logo

Cadence Design Systems

Hitachi Logo

Hitachi

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7 months ago
Technical
7 months ago
Can you describe how Immediate and Concurrent Assertions differ in SystemVerilog?
Design Verification Engineer
Verizon Logo

Verizon

Taiwan Semiconductor Logo

Taiwan Semiconductor

Novartis Logo

Novartis

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7 months ago

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*All interview questions are submitted by recent Verizon Design Verification Engineer candidates, labelled and categorized by Prepfully, and then published after being verified by Design Verification Engineers at Verizon.

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